Lines Matching refs:lo
214 msr.lo &= ~0xff000000; in initialize_vr_config()
217 msr.lo |= (min_vid & 0xff) << 24; in initialize_vr_config()
222 msr.lo &= ~0xffff; in initialize_vr_config()
228 msr.lo |= 0x006a; /* 1.56V */ in initialize_vr_config()
230 msr.lo |= 0x006f; /* 1.60V */ in initialize_vr_config()
345 perf_ctl.lo = (msr.lo & 0xff) << 8; in set_max_ratio()
349 perf_ctl.lo = (msr.lo & 0xff) << 8; in set_max_ratio()
353 perf_ctl.lo = msr.lo & 0xff00; in set_max_ratio()
358 ((perf_ctl.lo >> 8) & 0xff) * INTEL_BCLK_MHZ); in set_max_ratio()
370 num_threads = (msr.lo >> 0) & 0xffff; in broadwell_init()
371 num_cores = (msr.lo >> 16) & 0xffff; in broadwell_init()
394 num_banks = msr.lo & 0xff; in configure_mca()
395 msr.lo = 0; in configure_mca()
411 msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ in enable_lapic_tpr()
420 msr.lo |= (1 << 31); /* Timed MWAIT Enable */ in configure_c_states()
421 msr.lo |= (1 << 30); /* Package c-state Undemotion Enable */ in configure_c_states()
422 msr.lo |= (1 << 29); /* Package c-state Demotion Enable */ in configure_c_states()
423 msr.lo |= (1 << 28); /* C1 Auto Undemotion Enable */ in configure_c_states()
424 msr.lo |= (1 << 27); /* C3 Auto Undemotion Enable */ in configure_c_states()
425 msr.lo |= (1 << 26); /* C1 Auto Demotion Enable */ in configure_c_states()
426 msr.lo |= (1 << 25); /* C3 Auto Demotion Enable */ in configure_c_states()
427 msr.lo &= ~(1 << 10); /* Disable IO MWAIT redirection */ in configure_c_states()
432 msr.lo &= ~(1 << 0); /* Enable P-state HW_ALL coordination */ in configure_c_states()
436 msr.lo |= (1 << 18); /* Enable Energy Perf Bias MSR 0x1b0 */ in configure_c_states()
437 msr.lo |= (1 << 1); /* C1E Enable */ in configure_c_states()
438 msr.lo |= (1 << 0); /* Bi-directional PROCHOT# */ in configure_c_states()
443 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT; in configure_c_states()
448 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT; in configure_c_states()
453 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT; in configure_c_states()
458 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT; in configure_c_states()
463 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT; in configure_c_states()
468 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT; in configure_c_states()
477 msr.lo |= MISC_ENABLE_FAST_STRING; in configure_misc()
478 msr.lo |= MISC_ENABLE_TM1; in configure_misc()
479 msr.lo |= MISC_ENABLE_ENHANCED_SPEEDSTEP; in configure_misc()
483 msr.lo = 0; in configure_misc()
488 msr.lo = 1 << 4; in configure_misc()
502 msr.lo |= 1; in configure_dca_cap()
519 msr.lo &= ~0xf; in set_energy_perf_bias()
520 msr.lo |= policy & 0xf; in set_energy_perf_bias()
570 if (!(msr.lo & PLATFORM_INFO_SET_TDP)) in cpu_set_power_limits()
575 power_unit = 2 << ((msr.lo & 0xf) - 1); in cpu_set_power_limits()
579 tdp = msr.lo & 0x7fff; in cpu_set_power_limits()
580 min_power = (msr.lo >> 16) & 0x7fff; in cpu_set_power_limits()
598 limit.lo = 0; in cpu_set_power_limits()
599 limit.lo |= tdp & PKG_POWER_LIMIT_MASK; in cpu_set_power_limits()
600 limit.lo |= PKG_POWER_LIMIT_EN; in cpu_set_power_limits()
601 limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << in cpu_set_power_limits()
613 writel(limit.lo, MCHBAR_REG(MCH_PKG_POWER_LIMIT_LO)); in cpu_set_power_limits()
617 msr.lo = readl(MCHBAR_REG(MCH_DDR_POWER_LIMIT_LO)); in cpu_set_power_limits()
625 limit.lo = msr.lo & 0xff; in cpu_set_power_limits()