Lines Matching refs:msr_write
184 msr_write(MSR_VR_CURRENT_CONFIG, msr); in initialize_vr_config()
218 msr_write(MSR_VR_MISC_CONFIG, msr); in initialize_vr_config()
231 msr_write(MSR_VR_MISC_CONFIG2, msr); in initialize_vr_config()
355 msr_write(MSR_IA32_PERF_CTL, perf_ctl); in set_max_ratio()
403 msr_write(MSR_IA32_MC0_STATUS + (i * 4), msr); in configure_mca()
412 msr_write(MSR_PIC_MSG_CONTROL, msr); in enable_lapic_tpr()
429 msr_write(MSR_PMG_CST_CONFIG_CONTROL, msr); in configure_c_states()
433 msr_write(MSR_MISC_PWR_MGMT, msr); in configure_c_states()
439 msr_write(MSR_POWER_CTL, msr); in configure_c_states()
444 msr_write(MSR_C_STATE_LATENCY_CONTROL_0, msr); in configure_c_states()
449 msr_write(MSR_C_STATE_LATENCY_CONTROL_1, msr); in configure_c_states()
454 msr_write(MSR_C_STATE_LATENCY_CONTROL_2, msr); in configure_c_states()
459 msr_write(MSR_C_STATE_LATENCY_CONTROL_3, msr); in configure_c_states()
464 msr_write(MSR_C_STATE_LATENCY_CONTROL_4, msr); in configure_c_states()
469 msr_write(MSR_C_STATE_LATENCY_CONTROL_5, msr); in configure_c_states()
480 msr_write(MSR_IA32_MISC_ENABLE, msr); in configure_misc()
485 msr_write(MSR_IA32_THERM_INTERRUPT, msr); in configure_misc()
490 msr_write(MSR_IA32_PACKAGE_THERM_INTERRUPT, msr); in configure_misc()
503 msr_write(MSR_IA32_PLATFORM_DCA_CAP, msr); in configure_dca_cap()
521 msr_write(MSR_IA32_ENERGY_PERFORMANCE_BIAS, msr); in set_energy_perf_bias()
610 msr_write(MSR_PKG_POWER_LIMIT, limit); in cpu_set_power_limits()
619 msr_write(MSR_DDR_RAPL_LIMIT, msr); in cpu_set_power_limits()
626 msr_write(MSR_TURBO_ACTIVATION_RATIO, limit); in cpu_set_power_limits()