Lines Matching refs:reg8
133 u8 reg8; in pch_power_options() local
182 reg8 = inb(0x61); in pch_power_options()
183 reg8 &= 0x0f; /* Higher Nibble must be 0 */ in pch_power_options()
184 reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ in pch_power_options()
185 reg8 |= (1 << 2); /* PCI SERR# Disable for now */ in pch_power_options()
186 outb(reg8, 0x61); in pch_power_options()
188 reg8 = inb(0x70); in pch_power_options()
193 reg8 &= ~(1 << 7); /* Set NMI. */ in pch_power_options()
197 reg8 |= (1 << 7); in pch_power_options()
199 outb(reg8, 0x70); in pch_power_options()
240 u8 reg8; in pch_rtc_init() local
242 dm_pci_read_config8(pch, GEN_PMCON_3, ®8); in pch_rtc_init()
243 rtc_failed = reg8 & RTC_BATTERY_DEAD; in pch_rtc_init()
245 reg8 &= ~RTC_BATTERY_DEAD; in pch_rtc_init()
246 dm_pci_write_config8(pch, GEN_PMCON_3, reg8); in pch_rtc_init()
388 u8 reg8; in pch_disable_smm_only_flashing() local
391 dm_pci_read_config8(pch, 0xdc, ®8); /* BIOS_CNTL */ in pch_disable_smm_only_flashing()
392 reg8 &= ~(1 << 5); in pch_disable_smm_only_flashing()
393 dm_pci_write_config8(pch, 0xdc, reg8); in pch_disable_smm_only_flashing()