Lines Matching refs:ldr
22 ldr r0, =GPCR
23 ldr r1, =ACFG_GPCR_VAL
24 ldr r5, [r0]
31 ldr r0, =CSCR
33 ldr r1, [r0]
64 ldr r0, =IMX_ESD_BASE
65 ldr r4, =ESDMISC_SDRAM_RDY
66 2: ldr r1, [r0, #ESDMISC_ROF]
71 ldr r0, =IMX_ESD_BASE
72 ldr r4, =ACFG_ESDMISC_VAL
77 ldr r1, =0x10000
83 ldr r0, =IMX_ESD_BASE
84 ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL
87 ldr r0, =IMX_ESD_BASE
88 ldr r1, =ACFG_PRECHARGE_CMD
92 ldr r1, =PHYS_SDRAM_1+ACFG_SDRAM_PRECHARGE_ALL_VAL
95 ldr r1, =ACFG_AUTOREFRESH_CMD
98 ldr r4, =PHYS_SDRAM_1 /* CSD0 base address */
100 ldr r6,=0x7 /* load loop counter */
105 ldr r1, =ACFG_SET_MODE_REG_CMD
109 ldr r4, = PHYS_SDRAM_1+ACFG_SDRAM_MODE_REGISTER_VAL
113 ldr r4, =PHYS_SDRAM_1+ACFG_SDRAM_EXT_MODE_REGISTER_VAL
116 ldr r1, =ACFG_NORMAL_RW_CMD
120 ldr r0, =IMX_ESD_BASE
121 ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL
124 ldr r0, =IMX_ESD_BASE
125 ldr r1, =ACFG_PRECHARGE_CMD
129 ldr r1, =PHYS_SDRAM_2+ACFG_SDRAM_PRECHARGE_ALL_VAL
132 ldr r1, =ACFG_AUTOREFRESH_CMD
135 ldr r4, =PHYS_SDRAM_2 /* CSD1 base address */
137 ldr r6,=0x7 /* load loop counter */
142 ldr r1, =ACFG_SET_MODE_REG_CMD
146 ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_MODE_REGISTER_VAL
150 ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_EXT_MODE_REGISTER_VAL
153 ldr r1, =ACFG_NORMAL_RW_CMD