Lines Matching refs:bit3
35 # bit3-0: 0 required
52 # bit3-0: 1, 18 cycle tRAS (tRAS[3-0])
71 # bit3-2: 3, Cs0size=1Gb
89 # bit3-0: 0, Cmd=Normal SDRAM Mode
94 # bit3: 0, Burst Type (0 required)
116 # bit3: 1, MBUS Burst Chop disabled
127 # bit3-0: 0 required
135 # bit3-0: 2, 2 cycles from write comand to assertion of M_ODT signal
145 # bit3-2: 0x0, CS0 hit selected
153 # bit3-2: 1, CS1 hit selected
161 # bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM
170 # bit3-2: 0, M_ODT[1] assertion is controlled by ODT Control Low register
174 # bit3-0: 0b0011, internal ODT is asserted during read from DRAM bank 0-1