Lines Matching refs:MODE
35 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
36 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
41 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
42 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
43 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
44 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
45 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
46 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
51 {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */
52 {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
53 {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
54 {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
55 {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
56 {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
57 {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
58 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
59 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
60 {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */