Lines Matching refs:gpio_regs

32 	void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;  in ci20_mux_mmc()  local
35 writel(0x30f00000, gpio_regs + GPIO_PXINTC(4)); in ci20_mux_mmc()
36 writel(0x30f00000, gpio_regs + GPIO_PXMASKC(4)); in ci20_mux_mmc()
37 writel(0x30f00000, gpio_regs + GPIO_PXPAT1C(4)); in ci20_mux_mmc()
38 writel(0x30f00000, gpio_regs + GPIO_PXPAT0C(4)); in ci20_mux_mmc()
39 writel(0x30f00000, gpio_regs + GPIO_PXPENC(4)); in ci20_mux_mmc()
47 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; in ci20_mux_eth() local
51 writel(0x04030000, gpio_regs + GPIO_PXINTC(0)); in ci20_mux_eth()
52 writel(0x04030000, gpio_regs + GPIO_PXMASKC(0)); in ci20_mux_eth()
53 writel(0x04030000, gpio_regs + GPIO_PXPAT1C(0)); in ci20_mux_eth()
54 writel(0x04030000, gpio_regs + GPIO_PXPAT0C(0)); in ci20_mux_eth()
55 writel(0x04030000, gpio_regs + GPIO_PXPENS(0)); in ci20_mux_eth()
58 writel(0x0dff00ff, gpio_regs + GPIO_PXINTC(0)); in ci20_mux_eth()
59 writel(0x0dff00ff, gpio_regs + GPIO_PXMASKC(0)); in ci20_mux_eth()
60 writel(0x0dff00ff, gpio_regs + GPIO_PXPAT1C(0)); in ci20_mux_eth()
61 writel(0x0dff00ff, gpio_regs + GPIO_PXPAT0C(0)); in ci20_mux_eth()
62 writel(0x0dff00ff, gpio_regs + GPIO_PXPENS(0)); in ci20_mux_eth()
63 writel(0x00000003, gpio_regs + GPIO_PXINTC(1)); in ci20_mux_eth()
64 writel(0x00000003, gpio_regs + GPIO_PXMASKC(1)); in ci20_mux_eth()
65 writel(0x00000003, gpio_regs + GPIO_PXPAT1C(1)); in ci20_mux_eth()
66 writel(0x00000003, gpio_regs + GPIO_PXPAT0C(1)); in ci20_mux_eth()
67 writel(0x00000003, gpio_regs + GPIO_PXPENS(1)); in ci20_mux_eth()
74 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; in ci20_mux_jtag() local
77 writel(3 << 30, gpio_regs + GPIO_PXINTC(0)); in ci20_mux_jtag()
78 writel(3 << 30, gpio_regs + GPIO_PXMASKC(0)); in ci20_mux_jtag()
79 writel(3 << 30, gpio_regs + GPIO_PXPAT1C(0)); in ci20_mux_jtag()
80 writel(3 << 30, gpio_regs + GPIO_PXPAT0C(0)); in ci20_mux_jtag()
86 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; in ci20_mux_nand() local
89 writel(0x002c00ff, gpio_regs + GPIO_PXINTC(0)); in ci20_mux_nand()
90 writel(0x002c00ff, gpio_regs + GPIO_PXMASKC(0)); in ci20_mux_nand()
91 writel(0x002c00ff, gpio_regs + GPIO_PXPAT1C(0)); in ci20_mux_nand()
92 writel(0x002c00ff, gpio_regs + GPIO_PXPAT0C(0)); in ci20_mux_nand()
93 writel(0x002c00ff, gpio_regs + GPIO_PXPENS(0)); in ci20_mux_nand()
94 writel(0x00000003, gpio_regs + GPIO_PXINTC(1)); in ci20_mux_nand()
95 writel(0x00000003, gpio_regs + GPIO_PXMASKC(1)); in ci20_mux_nand()
96 writel(0x00000003, gpio_regs + GPIO_PXPAT1C(1)); in ci20_mux_nand()
97 writel(0x00000003, gpio_regs + GPIO_PXPAT0C(1)); in ci20_mux_nand()
98 writel(0x00000003, gpio_regs + GPIO_PXPENS(1)); in ci20_mux_nand()
102 writel(20, gpio_regs + GPIO_PXPENS(0)); in ci20_mux_nand()
110 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; in ci20_mux_uart() local
113 writel(0x9, gpio_regs + GPIO_PXINTC(5)); in ci20_mux_uart()
114 writel(0x9, gpio_regs + GPIO_PXMASKC(5)); in ci20_mux_uart()
115 writel(0x9, gpio_regs + GPIO_PXPAT1C(5)); in ci20_mux_uart()
116 writel(0x9, gpio_regs + GPIO_PXPAT0C(5)); in ci20_mux_uart()
117 writel(0x9, gpio_regs + GPIO_PXPENC(5)); in ci20_mux_uart()
126 writel(1 << 12, gpio_regs + GPIO_PXINTC(3)); in ci20_mux_uart()
127 writel(1 << 12, gpio_regs + GPIO_PXMASKS(3)); in ci20_mux_uart()
128 writel(1 << 12, gpio_regs + GPIO_PXPAT1S(3)); in ci20_mux_uart()
129 writel(1 << 12, gpio_regs + GPIO_PXPAT0C(3)); in ci20_mux_uart()
130 writel(3 << 30, gpio_regs + GPIO_PXINTC(0)); in ci20_mux_uart()
131 writel(3 << 30, gpio_regs + GPIO_PXMASKC(0)); in ci20_mux_uart()
132 writel(3 << 30, gpio_regs + GPIO_PXPAT1C(0)); in ci20_mux_uart()
133 writel(1 << 30, gpio_regs + GPIO_PXPAT0C(0)); in ci20_mux_uart()
134 writel(1 << 31, gpio_regs + GPIO_PXPAT0S(0)); in ci20_mux_uart()
139 writel(0x100400, gpio_regs + GPIO_PXINTC(2)); in ci20_mux_uart()
140 writel(0x100400, gpio_regs + GPIO_PXMASKC(2)); in ci20_mux_uart()
141 writel(0x100400, gpio_regs + GPIO_PXPAT1S(2)); in ci20_mux_uart()
142 writel(0x100400, gpio_regs + GPIO_PXPAT0C(2)); in ci20_mux_uart()
143 writel(0x100400, gpio_regs + GPIO_PXPENC(2)); in ci20_mux_uart()
221 void __iomem *gpio_regs = (void __iomem *)GPIO_BASE; in ci20_revision() local
228 writel(BIT(18) | BIT(19), gpio_regs + GPIO_PXPENC(2)); in ci20_revision()