Lines Matching refs:li
38 li t1, MALTA_REVISION_CORID_CORE_LV
42 li t1, MALTA_REVISION_CORID_CORE_FPGA6
66 li t0, CPU_TO_GT32(0xdf000000)
73 li t0, CPU_TO_GT32(0xc0000000)
75 li t0, CPU_TO_GT32(0x40000000)
79 li t0, CPU_TO_GT32(0x80000000)
81 li t0, CPU_TO_GT32(0x3f000000)
84 li t0, CPU_TO_GT32(0xc1000000)
86 li t0, CPU_TO_GT32(0x5e000000)
98 li t1, 0x1 << MSC01_PBC_CLKCFG_SHF
102 li t1, (0x1 << MSC01_PBC_CS0TIM_CDT_SHF) | \
105 li t1, (0x0 << MSC01_PBC_CS0RW_RDT_SHF) | \
111 li t2, MSC01_PBC_CS0CFG_DTYP_MSK
120 li t1, 0x0
121 li t2, -CONFIG_SYS_MEM_SIZE
128 li t1, MALTA_MSC01_IP1_BASE
129 li t2, -MALTA_MSC01_IP1_SIZE
136 li t1, MALTA_MSC01_IP2_BASE1
137 li t2, -MALTA_MSC01_IP2_SIZE1
140 li t1, MALTA_MSC01_IP2_BASE2
141 li t2, -MALTA_MSC01_IP2_SIZE2
146 li t1, MALTA_MSC01_IP3_BASE
147 li t2, -MALTA_MSC01_IP3_SIZE
155 li t1, MALTA_MSC01_PCIMEM_BASE
156 li t2, (-MALTA_MSC01_PCIMEM_SIZE) & MSC01_PCI_SC2PMMSKL_MSK_MSK
157 li t3, MALTA_MSC01_PCIMEM_MAP
163 li t1, MALTA_MSC01_PCIIO_BASE
164 li t2, (-MALTA_MSC01_PCIIO_SIZE) & MSC01_PCI_SC2PIOMSKL_MSK_MSK
165 li t3, MALTA_MSC01_PCIIO_MAP
171 li t1, -CONFIG_SYS_MEM_SIZE
179 li t1, (PCI_VENDOR_ID_MIPS << MSC01_PCI_HEAD0_VENDORID_SHF) | \
187 li t1, (PCI_CLASS_BRIDGE_HOST << MSC01_PCI_HEAD2_CLASS_SHF) | \
206 li t1, (PCI_COMMAND_FAST_BACK | \
215 li t1, (0x1 << MSC01_PCI_SWAP_BAR0_BSWAP_SHF) | \
224 li t2, MSC01_PCI_CFG_RA_MSK | \