Lines Matching refs:DIV_STAT_CHANGING
56 #define DIV_STAT_CHANGING 0x1 macro
57 #define DIV_STAT_CPU0_CHANGING (DIV_CORE(DIV_STAT_CHANGING) | \
58 DIV_COREM0(DIV_STAT_CHANGING) | \
59 DIV_COREM1(DIV_STAT_CHANGING) | \
60 DIV_PERIPH(DIV_STAT_CHANGING) | \
61 DIV_ATB(DIV_STAT_CHANGING) | \
62 DIV_PCLK_DBG(DIV_STAT_CHANGING) | \
63 DIV_APLL(DIV_STAT_CHANGING) | \
64 DIV_CORE2(DIV_STAT_CHANGING))
76 #define DIV_STAT_CPU1_CHANGING (DIV_COPY(DIV_STAT_CHANGING) | \
77 DIV_HPM(DIV_STAT_CHANGING) | \
78 DIV_CORES(DIV_STAT_CHANGING))
124 #define DIV_STAT_DMC0_CHANGING (DIV_ACP(DIV_STAT_CHANGING) | \
125 DIV_ACP_PCLK(DIV_STAT_CHANGING) | \
126 DIV_DPHY(DIV_STAT_CHANGING) | \
127 DIV_DMC(DIV_STAT_CHANGING) | \
128 DIV_DMCD(DIV_STAT_CHANGING) | \
129 DIV_DMCP(DIV_STAT_CHANGING))
147 #define DIV_STAT_DMC1_CHANGING (DIV_G2D_ACP(DIV_STAT_CHANGING) | \
148 DIV_C2C(DIV_STAT_CHANGING) | \
149 DIV_PWI(DIV_STAT_CHANGING) | \
150 DIV_C2C_ACLK(DIV_STAT_CHANGING) | \
151 DIV_DVSEM(DIV_STAT_CHANGING) | \
152 DIV_DPM(DIV_STAT_CHANGING))
175 #define DIV_STAT_PERIL0_CHANGING (DIV_UART4(DIV_STAT_CHANGING) | \
176 DIV_UART3(DIV_STAT_CHANGING) | \
177 DIV_UART2(DIV_STAT_CHANGING) | \
178 DIV_UART1(DIV_STAT_CHANGING) | \
179 DIV_UART0(DIV_STAT_CHANGING))
193 #define DIV_STAT_FSYS1_CHANGING (DIV_MMC0(DIV_STAT_CHANGING) | \
194 DIV_MMC0_PRE(DIV_STAT_CHANGING) | \
195 DIV_MMC1(DIV_STAT_CHANGING) | \
196 DIV_MMC1_PRE(DIV_STAT_CHANGING))
210 #define DIV_STAT_FSYS2_CHANGING (DIV_MMC2(DIV_STAT_CHANGING) | \
211 DIV_MMC2_PRE(DIV_STAT_CHANGING) | \
212 DIV_MMC3(DIV_STAT_CHANGING) | \
213 DIV_MMC3_PRE(DIV_STAT_CHANGING))
223 #define DIV_STAT_FSYS3_CHANGING (DIV_MMC4(DIV_STAT_CHANGING) | \
224 DIV_MMC4_PRE(DIV_STAT_CHANGING))