Lines Matching refs:MMDC_P1_BASE_ADDR
327 writel(0x00000004, MMDC_P1_BASE_ADDR + 0x80c); in spl_dram_init_imx6qp_lpddr3()
328 writel(0x00000000, MMDC_P1_BASE_ADDR + 0x810); in spl_dram_init_imx6qp_lpddr3()
335 writel(0x03000310, MMDC_P1_BASE_ADDR + 0x83c); in spl_dram_init_imx6qp_lpddr3()
336 writel(0x0268023C, MMDC_P1_BASE_ADDR + 0x840); in spl_dram_init_imx6qp_lpddr3()
338 writel(0x36302C3C, MMDC_P1_BASE_ADDR + 0x848); in spl_dram_init_imx6qp_lpddr3()
340 writel(0x483A4844, MMDC_P1_BASE_ADDR + 0x850); in spl_dram_init_imx6qp_lpddr3()
345 writel(0x33333333, MMDC_P1_BASE_ADDR + 0x81c); in spl_dram_init_imx6qp_lpddr3()
346 writel(0x33333333, MMDC_P1_BASE_ADDR + 0x820); in spl_dram_init_imx6qp_lpddr3()
347 writel(0x33333333, MMDC_P1_BASE_ADDR + 0x824); in spl_dram_init_imx6qp_lpddr3()
348 writel(0x33333333, MMDC_P1_BASE_ADDR + 0x828); in spl_dram_init_imx6qp_lpddr3()
350 writel(0x24914452, MMDC_P1_BASE_ADDR + 0x8c0); in spl_dram_init_imx6qp_lpddr3()
352 writel(0x00000800, MMDC_P1_BASE_ADDR + 0x8b8); in spl_dram_init_imx6qp_lpddr3()
381 writel(0x00022227, MMDC_P1_BASE_ADDR + 0x818); in spl_dram_init_imx6qp_lpddr3()