Lines Matching refs:or
5 For some PowerPC processors with SRIO or PCIE interface, boot location can be
6 configured to SRIO or PCIE by RCW. The processor booting from SRIO or PCIE can
8 from another processor's memory space by SRIO or PCIE link connected between
12 platforms and a RCW example with boot from SRIO or PCIE configuration.
14 Environment of the SRIO or PCIE boot:
15 a) Master and slave can be SOCs in one board or SOCs in separate boards.
16 b) They are connected with SRIO or PCIE links, whether 1x, 2x or 4x, and
17 directly or through switch system.
21 e) Slave's RCW should configure the SerDes for SRIO or PCIE boot port, set
22 the boot location to SRIO or PCIE, and holdoff all the cores.
27 | NorFlash|<----->| Master |SRIO or PCIE | Slave |<---->[EEPROM]
33 Two P4080DS platforms can be used to implement the boot from SRIO or PCIE.
34 Their SRIO or PCIE ports 1 will be connected directly and will be used for
35 the boot from SRIO or PCIE.
52 a) Update RCW for slave with boot from SRIO or PCIE port 1 configuration.
55 c) Set environment variable "bootmaster" to "SRIO1" or "PCIE1" and save
58 or
63 SRIO or PCIE port 1.
64 e) Master will set inbound SRIO or PCIE windows covered slave's U-Boot
66 f) Master will set an inbound SRIO or PCIE window covered slave's UCode
68 g) Master will set outbound SRIO or PCIE windows in order to configure
72 startup phase of the slave from SRIO or PCIE, it will finish some
75 j) Slave will set a LAW entry with the TargetID SRIO or PCIE port 1 for
79 l) Slave will set a LAW entry with the TargetID SRIO or PCIE port 1 for
85 1. Slave's RCW with SRIO or PCIE boot configurations, and all cores in holdoff
111 or "PCIE1", "PCIE2", "PCIE3" for master, and then restart it in order to
112 perform the role as a master for boot from SRIO or PCIE.
115 it can fetch them through PCIE or SRIO interface. But the ENV
116 parameters can not be modified by "saveenv" or other commands under
118 write Master's NorFlash by PCIE or SRIO link.