Lines Matching refs:or
5 in single, continuous, scan or discontinuous mode. Result of the ADC is
6 stored in a left-aligned or right-aligned 32-bit data register.
7 Conversions can be launched in software or using hardware triggers.
10 voltage goes beyond the user-defined, higher or lower thresholds.
18 interrupt regular conversion sequence (either triggered in SW or HW).
29 - interrupts: One or more interrupts for ADC block. Some parts like stm32f4
39 - clock-names: Must be "adc" and/or "bus" depending on part used.
64 - interrupts: IRQ Line for the ADC (e.g. may be 0 for adc@0, 1 for adc@100 or
67 It can have up to 16 channels on stm32f4 or 20 channels on stm32h7, numbered
68 from 0 to 15 or 19 (resp. for in0..in15 or in0..in19).
74 Note: At least one of "st,adc-channels" or "st,adc-diff-channels" is required.
87 * can be 6, 8, 10 or 12 on stm32f4
88 * can be 8, 10, 12, 14 or 16 on stm32h7
93 This can be either one value or an array that matches 'st,adc-channels' list,
94 to set sample time resp. for all channels, or independently for each channel.