Lines Matching refs:L2
1 * ARM L2 Cache Controller
5 of the L2 cache controller have compatible programming models (Note 1).
10 The ARM L2 cache representation in the device tree should be done as follows:
20 offset needs to be added to the address before passing down to the L2
24 maintenance operations on L1 are broadcasted to the L2 and L2
60 - wt-override: If present then L2 is forced to Write through mode
77 - arm,parity-enable : enable parity checking on the L2 cache (L220 or PL310).
78 - arm,parity-disable : disable parity checking on the L2 cache (L220 or PL310).
79 - arm,outer-sync-disable : disable the outer sync operation on the L2 cache.
87 - arm,dynamic-clock-gating : L2 dynamic clock gating. Value: <0> (forcibly
90 - arm,standby-mode: L2 standby mode enable. Value <0> (forcibly disable),
99 L2: cache-controller {
110 Note 1: The description in this document doesn't apply to integrated L2
112 integrated L2 controllers are assumed to be all preconfigured by