Lines Matching refs:GPIO
1 NVIDIA Tegra186 GPIO controllers
3 Tegra186 contains two GPIO controllers; a main controller and an "AON"
9 The Tegra186 GPIO controller allows software to set the IO direction of, and
10 read/write the value of, numerous GPIO signals. Routing of GPIO signals to
14 a) Security registers, which allow configuration of allowed access to the GPIO
17 varies between the different GPIO controllers.
20 that wishes to configure access to the GPIO registers needs access to these
21 registers to do so. Code which simply wishes to read or write GPIO data does not
24 b) GPIO registers, which allow manipulation of the GPIO signals. In some GPIO
27 documentation for rationale. Any particular GPIO client is expected to access
31 implemented by the SoC. Each GPIO is assigned to a port, and a port may control
32 a number of GPIOs. Thus, each GPIO is named according to an alphabetical port
33 name and an integer GPIO name within the port. For example, GPIO_PA0, GPIO_PN6,
36 The number of ports implemented by each GPIO controller varies. The number of
37 implemented GPIOs within each port varies. GPIO registers within a controller
40 The mapping from port name to the GPIO controller that implements that port, and
45 sorted within a particular controller. Drivers need to map between the DT GPIO
48 Each GPIO controller can generate a number of interrupt signals. Each signal
54 Each GPIO controller in fact generates multiple interrupts signals for each set
55 of ports. Each GPIO may be configured to feed into a specific one of the
75 - "gpio": Mandatory. GPIO control registers. This may cover either:
96 Marks the device node as a GPIO controller/provider.
100 Indicates how many cells are used in a consumer's GPIO specifier.
116 - The first cell is the GPIO number.