Lines Matching refs:port_mmio
117 void __iomem *port_mmio = uc_priv->port[port].port_mmio; in ahci_link_up() local
125 tmp = readl(port_mmio + PORT_SCR_STAT); in ahci_link_up()
137 static void sunxi_dma_init(void __iomem *port_mmio) in sunxi_dma_init() argument
139 clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400); in sunxi_dma_init()
185 void __iomem *port_mmio; in ahci_host_init() local
237 uc_priv->port[i].port_mmio = ahci_port_base(mmio, i); in ahci_host_init()
238 port_mmio = (u8 *)uc_priv->port[i].port_mmio; in ahci_host_init()
241 tmp = readl(port_mmio + PORT_CMD); in ahci_host_init()
247 writel_with_flush(tmp, port_mmio + PORT_CMD); in ahci_host_init()
256 sunxi_dma_init(port_mmio); in ahci_host_init()
262 cmd = readl(port_mmio + PORT_CMD); in ahci_host_init()
264 writel_with_flush(cmd, port_mmio + PORT_CMD); in ahci_host_init()
276 tmp = readl(port_mmio + PORT_SCR_ERR); in ahci_host_init()
278 writel(tmp, port_mmio + PORT_SCR_ERR); in ahci_host_init()
284 tmp = readl(port_mmio + PORT_TFDATA); in ahci_host_init()
288 tmp = readl(port_mmio + PORT_SCR_STAT); in ahci_host_init()
295 tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK; in ahci_host_init()
308 tmp = readl(port_mmio + PORT_SCR_ERR); in ahci_host_init()
310 writel(tmp, port_mmio + PORT_SCR_ERR); in ahci_host_init()
313 tmp = readl(port_mmio + PORT_IRQ_STAT); in ahci_host_init()
316 writel(tmp, port_mmio + PORT_IRQ_STAT); in ahci_host_init()
321 tmp = readl(port_mmio + PORT_SCR_STAT); in ahci_host_init()
545 static int wait_spinup(void __iomem *port_mmio) in wait_spinup() argument
552 tf_data = readl(port_mmio + PORT_TFDATA); in wait_spinup()
563 void __iomem *port_mmio = pp->port_mmio; in ahci_port_start() local
569 port_status = readl(port_mmio + PORT_SCR_STAT); in ahci_port_start()
611 writel_with_flush(dma_addr, port_mmio + PORT_LST_ADDR); in ahci_port_start()
612 writel_with_flush(dma_addr >> 32, port_mmio + PORT_LST_ADDR_HI); in ahci_port_start()
614 writel_with_flush(dma_addr, port_mmio + PORT_FIS_ADDR); in ahci_port_start()
615 writel_with_flush(dma_addr >> 32, port_mmio + PORT_FIS_ADDR_HI); in ahci_port_start()
618 sunxi_dma_init(port_mmio); in ahci_port_start()
623 PORT_CMD_START, port_mmio + PORT_CMD); in ahci_port_start()
631 return wait_spinup(port_mmio); in ahci_port_start()
640 void __iomem *port_mmio = pp->port_mmio; in ahci_device_data_io() local
652 port_status = readl(port_mmio + PORT_SCR_STAT); in ahci_device_data_io()
667 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); in ahci_device_data_io()
669 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, in ahci_device_data_io()
1119 void __iomem *port_mmio = pp->port_mmio; in ata_io_flush() local
1131 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); in ata_io_flush()
1133 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, in ata_io_flush()