Lines Matching refs:CM_REG_READL
119 req_status = CM_REG_READL(plat, CLKMGR_MAINPLL_MEM); in membus_wait_for_req()
121 req_status = CM_REG_READL(plat, CLKMGR_PERPLL_MEM); in membus_wait_for_req()
125 req_status = CM_REG_READL(plat, CLKMGR_MAINPLL_MEM); in membus_wait_for_req()
127 req_status = CM_REG_READL(plat, CLKMGR_PERPLL_MEM); in membus_wait_for_req()
179 *rdata = CM_REG_READL(plat, CLKMGR_MAINPLL_MEMSTAT); in membus_read_pll()
181 *rdata = CM_REG_READL(plat, CLKMGR_PERPLL_MEMSTAT); in membus_read_pll()
249 CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE); in clk_basic_init()
252 if (!(CM_REG_READL(plat, CLKMGR_CTRL) & CLKMGR_CTRL_BOOTMODE)) in clk_basic_init()
321 CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_MAINPLL_PLLGLOB) | in clk_basic_init()
324 CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_PERPLL_PLLGLOB) | in clk_basic_init()
343 CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE); in clk_basic_init()
351 reg = CM_REG_READL(plat, pllglob_reg); in clk_get_vco_clk_hz()
371 mdiv = CM_REG_READL(plat, pllm_reg) & CLKMGR_PLLM_MDIV_MASK; in clk_get_vco_clk_hz()
393 u32 clksrc = CM_REG_READL(plat, reg); in clk_get_5_1_clk_src()
407 clock /= (CM_REG_READL(plat, main_reg) & in clk_get_clksrc_hz()
413 clock /= (CM_REG_READL(plat, per_reg) & in clk_get_clksrc_hz()
441 clock /= 1 + (CM_REG_READL(plat, CLKMGR_MAINPLL_MPUCLK) & in clk_get_mpu_clk_hz()
458 clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >> in clk_get_l4_main_clk_hz()
471 clock /= 1 + (CM_REG_READL(plat, CLKMGR_ALTR_SDMMCCTR) & in clk_get_sdmmc_clk_hz()
481 clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >> in clk_get_l4_sp_clk_hz()
492 clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >> in clk_get_l4_mp_clk_hz()
501 if (CM_REG_READL(plat, CLKMGR_STAT) & CLKMGR_STAT_BOOTMODE) in clk_get_l4_sys_free_clk_hz()
517 ctl = CM_REG_READL(plat, CLKMGR_PERPLL_EMACCTL); in clk_get_emac_clk_hz()
540 reg = CM_REG_READL(plat, ctr_reg); in clk_get_emac_clk_hz()
550 clock /= (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC2) & in clk_get_emac_clk_hz()
553 clock /= (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC3) & in clk_get_emac_clk_hz()
561 clock /= (CM_REG_READL(plat, CLKMGR_PERPLL_PLLC2) & in clk_get_emac_clk_hz()
564 clock /= (CM_REG_READL(plat, CLKMGR_PERPLL_PLLC3) & in clk_get_emac_clk_hz()