Lines Matching refs:pll
97 struct sam9x60_pll *pll = to_sam9x60_pll(clk); in sam9x60_frac_pll_set_rate() local
98 void __iomem *base = pll->base; in sam9x60_frac_pll_set_rate()
101 bool ready = sam9x60_pll_ready(base, pll->id); in sam9x60_frac_pll_set_rate()
113 pll->id); in sam9x60_frac_pll_set_rate()
115 cmul = (val & pll->layout->mul_mask) >> pll->layout->mul_shift; in sam9x60_frac_pll_set_rate()
116 cfrac = (val & pll->layout->frac_mask) >> pll->layout->frac_shift; in sam9x60_frac_pll_set_rate()
119 if (sam9x60_pll_ready(base, pll->id) && in sam9x60_frac_pll_set_rate()
125 (nmul << pll->layout->mul_shift) | in sam9x60_frac_pll_set_rate()
126 (nfrac << pll->layout->frac_shift)); in sam9x60_frac_pll_set_rate()
130 AT91_PMC_PLL_UPDT_UPDATE | pll->id); in sam9x60_frac_pll_set_rate()
132 while (ready && !sam9x60_pll_ready(base, pll->id)) { in sam9x60_frac_pll_set_rate()
133 debug("waiting for pll %u...\n", pll->id); in sam9x60_frac_pll_set_rate()
142 struct sam9x60_pll *pll = to_sam9x60_pll(clk); in sam9x60_frac_pll_get_rate() local
143 void __iomem *base = pll->base; in sam9x60_frac_pll_get_rate()
151 pll->id); in sam9x60_frac_pll_get_rate()
153 mul = (val & pll->layout->mul_mask) >> pll->layout->mul_shift; in sam9x60_frac_pll_get_rate()
154 frac = (val & pll->layout->frac_mask) >> pll->layout->frac_shift; in sam9x60_frac_pll_get_rate()
161 struct sam9x60_pll *pll = to_sam9x60_pll(clk); in sam9x60_frac_pll_enable() local
162 void __iomem *base = pll->base; in sam9x60_frac_pll_enable()
171 pll->id); in sam9x60_frac_pll_enable()
174 if (sam9x60_pll_ready(base, pll->id)) in sam9x60_frac_pll_enable()
180 AT91_PMC_PLL_UPDT_STUPTIM(0x3f) | pll->id); in sam9x60_frac_pll_enable()
183 if (pll->characteristics->upll) in sam9x60_frac_pll_enable()
189 if (pll->characteristics->upll) { in sam9x60_frac_pll_enable()
205 AT91_PMC_PLL_UPDT_UPDATE | pll->id); in sam9x60_frac_pll_enable()
214 AT91_PMC_PLL_UPDT_UPDATE | pll->id); in sam9x60_frac_pll_enable()
216 while (!sam9x60_pll_ready(base, pll->id)) { in sam9x60_frac_pll_enable()
217 debug("waiting for pll %u...\n", pll->id); in sam9x60_frac_pll_enable()
226 struct sam9x60_pll *pll = to_sam9x60_pll(clk); in sam9x60_frac_pll_disable() local
227 void __iomem *base = pll->base; in sam9x60_frac_pll_disable()
230 pll->id); in sam9x60_frac_pll_disable()
235 if (pll->characteristics->upll) in sam9x60_frac_pll_disable()
242 AT91_PMC_PLL_UPDT_UPDATE | pll->id); in sam9x60_frac_pll_disable()
256 struct sam9x60_pll *pll = to_sam9x60_pll(clk); in sam9x60_div_pll_enable() local
257 void __iomem *base = pll->base; in sam9x60_div_pll_enable()
261 pll->id); in sam9x60_div_pll_enable()
265 if (val & pll->layout->endiv_mask) in sam9x60_div_pll_enable()
269 pll->layout->endiv_mask, in sam9x60_div_pll_enable()
270 (1 << pll->layout->endiv_shift)); in sam9x60_div_pll_enable()
274 AT91_PMC_PLL_UPDT_UPDATE | pll->id); in sam9x60_div_pll_enable()
276 while (!sam9x60_pll_ready(base, pll->id)) { in sam9x60_div_pll_enable()
277 debug("waiting for pll %u...\n", pll->id); in sam9x60_div_pll_enable()
286 struct sam9x60_pll *pll = to_sam9x60_pll(clk); in sam9x60_div_pll_disable() local
287 void __iomem *base = pll->base; in sam9x60_div_pll_disable()
290 pll->id); in sam9x60_div_pll_disable()
293 pll->layout->endiv_mask, 0); in sam9x60_div_pll_disable()
297 AT91_PMC_PLL_UPDT_UPDATE | pll->id); in sam9x60_div_pll_disable()
304 struct sam9x60_pll *pll = to_sam9x60_pll(clk); in sam9x60_div_pll_set_rate() local
305 void __iomem *base = pll->base; in sam9x60_div_pll_set_rate()
307 pll->characteristics; in sam9x60_div_pll_set_rate()
311 bool ready = sam9x60_pll_ready(base, pll->id); in sam9x60_div_pll_set_rate()
314 if (!parent_rate || div > pll->layout->div_mask || in sam9x60_div_pll_set_rate()
320 pll->id); in sam9x60_div_pll_set_rate()
323 if (div == ((val & pll->layout->div_mask) >> pll->layout->div_shift)) in sam9x60_div_pll_set_rate()
328 pll->layout->div_mask, in sam9x60_div_pll_set_rate()
329 div << pll->layout->div_shift); in sam9x60_div_pll_set_rate()
333 AT91_PMC_PLL_UPDT_UPDATE | pll->id); in sam9x60_div_pll_set_rate()
335 while (ready && !sam9x60_pll_ready(base, pll->id)) { in sam9x60_div_pll_set_rate()
336 debug("waiting for pll %u...\n", pll->id); in sam9x60_div_pll_set_rate()
345 struct sam9x60_pll *pll = to_sam9x60_pll(clk); in sam9x60_div_pll_get_rate() local
346 void __iomem *base = pll->base; in sam9x60_div_pll_get_rate()
355 pll->id); in sam9x60_div_pll_get_rate()
359 div = (val & pll->layout->div_mask) >> pll->layout->div_shift; in sam9x60_div_pll_get_rate()
377 struct sam9x60_pll *pll; in sam9x60_clk_register_pll() local
385 pll = kzalloc(sizeof(*pll), GFP_KERNEL); in sam9x60_clk_register_pll()
386 if (!pll) in sam9x60_clk_register_pll()
389 pll->id = id; in sam9x60_clk_register_pll()
390 pll->characteristics = characteristics; in sam9x60_clk_register_pll()
391 pll->layout = layout; in sam9x60_clk_register_pll()
392 pll->base = base; in sam9x60_clk_register_pll()
393 clk = &pll->clk; in sam9x60_clk_register_pll()
398 kfree(pll); in sam9x60_clk_register_pll()