Lines Matching defs:stm32_rcc_regs
124 struct stm32_rcc_regs { struct
125 u32 cr; /* 0x00 Source Control Register */
126 u32 icscr; /* 0x04 Internal Clock Source Calibration Register */
127 u32 crrcr; /* 0x08 Clock Recovery RC Register */
128 u32 reserved1; /* 0x0c reserved */
129 u32 cfgr; /* 0x10 Clock Configuration Register */
130 u32 reserved2; /* 0x14 reserved */
131 u32 d1cfgr; /* 0x18 Domain 1 Clock Configuration Register */
132 u32 d2cfgr; /* 0x1c Domain 2 Clock Configuration Register */
133 u32 d3cfgr; /* 0x20 Domain 3 Clock Configuration Register */
134 u32 reserved3; /* 0x24 reserved */
135 u32 pllckselr; /* 0x28 PLLs Clock Source Selection Register */
136 u32 pllcfgr; /* 0x2c PLLs Configuration Register */
137 u32 pll1divr; /* 0x30 PLL1 Dividers Configuration Register */
138 u32 pll1fracr; /* 0x34 PLL1 Fractional Divider Register */
139 u32 pll2divr; /* 0x38 PLL2 Dividers Configuration Register */
140 u32 pll2fracr; /* 0x3c PLL2 Fractional Divider Register */
141 u32 pll3divr; /* 0x40 PLL3 Dividers Configuration Register */
142 u32 pll3fracr; /* 0x44 PLL3 Fractional Divider Register */
143 u32 reserved4; /* 0x48 reserved */
144 u32 d1ccipr; /* 0x4c Domain 1 Kernel Clock Configuration Register */
145 u32 d2ccip1r; /* 0x50 Domain 2 Kernel Clock Configuration Register */
146 u32 d2ccip2r; /* 0x54 Domain 2 Kernel Clock Configuration Register */
147 u32 d3ccipr; /* 0x58 Domain 3 Kernel Clock Configuration Register */
148 u32 reserved5; /* 0x5c reserved */
149 u32 cier; /* 0x60 Clock Source Interrupt Enable Register */
150 u32 cifr; /* 0x64 Clock Source Interrupt Flag Register */
151 u32 cicr; /* 0x68 Clock Source Interrupt Clear Register */
152 u32 reserved6; /* 0x6c reserved */
153 u32 bdcr; /* 0x70 Backup Domain Control Register */
154 u32 csr; /* 0x74 Clock Control and Status Register */
155 u32 reserved7; /* 0x78 reserved */
157 u32 ahb3rstr; /* 0x7c AHB3 Peripheral Reset Register */
158 u32 ahb1rstr; /* 0x80 AHB1 Peripheral Reset Register */
159 u32 ahb2rstr; /* 0x84 AHB2 Peripheral Reset Register */
160 u32 ahb4rstr; /* 0x88 AHB4 Peripheral Reset Register */
185 #define RCC_AHB3ENR offsetof(struct stm32_rcc_regs, ahb3enr) argument