clk_stm32h7.c - OpenGrok cross reference for /u-boot/drivers/clk/clk

Lines Matching refs:pll1divr

137 	u32 pll1divr;	/* 0x30 PLL1 Dividers Configuration Register */  member
356 	uint32_t pll1divr = 0;  in configure_clocks()  local
402 	pll1divr |= (sys_pll_psc.divr - 1) << RCC_PLL1DIVR_DIVR1_SHIFT;  in configure_clocks()
403 	pll1divr |= (sys_pll_psc.divq - 1) << RCC_PLL1DIVR_DIVQ1_SHIFT;  in configure_clocks()
404 	pll1divr |= (sys_pll_psc.divp - 1) << RCC_PLL1DIVR_DIVP1_SHIFT;  in configure_clocks()
405 	pll1divr |= (sys_pll_psc.divn - 1);  in configure_clocks()
406 	writel(pll1divr, &regs->pll1divr);  in configure_clocks()
534 	divn1 = (readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVN1_MASK) + 1;  in stm32_get_PLL1_rate()
536 	divp1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVP1_MASK;  in stm32_get_PLL1_rate()
539 	divq1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVQ1_MASK;  in stm32_get_PLL1_rate()
542 	divr1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK;  in stm32_get_PLL1_rate()