Lines Matching refs:divn
903 int divm, divn; in pll_get_fvco() local
911 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; in pll_get_fvco()
924 (((divn + 1) << 13) + fracv), in pll_get_fvco()
927 fvco = (ulong)(refclk * (divn + 1) / (divm + 1)); in pll_get_fvco()
1324 u32 divm, divn, divp, frac; in stm32mp1_pll1_opp() local
1363 divn = (u32)((freq / input_freq) - 1); in stm32mp1_pll1_opp()
1364 if (divn < DIVN_MIN || divn > DIVN_MAX) in stm32mp1_pll1_opp()
1368 ((divn + 1) * FRAC_MAX)); in stm32mp1_pll1_opp()
1374 vco = (post_divm * (divn + 1)) + in stm32mp1_pll1_opp()
1389 pllcfg[PLLCFG_N] = divn; in stm32mp1_pll1_opp()
1698 int divm, divn, divy; in pll_set_rate() local
1734 divn = (value >> 13) - 1; in pll_set_rate()
1735 if (divn < DIVN_MIN || in pll_set_rate()
1736 divn > stm32mp1_pll[type].divn_max) { in pll_set_rate()
1737 dev_err(dev, "divn invalid = %d", divn); in pll_set_rate()
1740 fracv = value - ((divn + 1) << 13); in pll_set_rate()
1741 pllcfg[PLLCFG_N] = divn; in pll_set_rate()