Lines Matching refs:clk_id
96 u32 clk_id; member
139 static inline int versal_is_valid_clock(u32 clk_id) in versal_is_valid_clock() argument
141 if (clk_id >= clock_max_idx) in versal_is_valid_clock()
144 return clock[clk_id].valid; in versal_is_valid_clock()
147 static int versal_get_clock_name(u32 clk_id, char *clk_name) in versal_get_clock_name() argument
151 ret = versal_is_valid_clock(clk_id); in versal_get_clock_name()
153 strncpy(clk_name, clock[clk_id].clk_name, MAX_NAME_LEN); in versal_get_clock_name()
160 static int versal_get_clock_type(u32 clk_id, u32 *type) in versal_get_clock_type() argument
164 ret = versal_is_valid_clock(clk_id); in versal_get_clock_type()
166 *type = clock[clk_id].type; in versal_get_clock_type()
276 static int versal_clock_get_topology(u32 clk_id, in versal_clock_get_topology() argument
285 ret = versal_pm_clock_get_topology(clock[clk_id].clk_id, j, in versal_clock_get_topology()
324 static int versal_clock_get_parents(u32 clk_id, struct clock_parent *parents, in versal_clock_get_parents() argument
333 ret = versal_pm_clock_get_parents(clock[clk_id].clk_id, j, in versal_clock_get_parents()
348 static u32 versal_clock_get_div(u32 clk_id) in versal_clock_get_div() argument
353 xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload); in versal_clock_get_div()
359 static u32 versal_clock_set_div(u32 clk_id, u32 div) in versal_clock_set_div() argument
363 xilinx_pm_request(PM_CLOCK_SETDIVIDER, clk_id, div, 0, 0, ret_payload); in versal_clock_set_div()
368 static u64 versal_clock_ref(u32 clk_id) in versal_clock_ref() argument
373 xilinx_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, ret_payload); in versal_clock_ref()
382 static u64 versal_clock_get_pll_rate(u32 clk_id) in versal_clock_get_pll_rate() argument
390 u32 id = clk_id & 0xFFF; in versal_clock_get_pll_rate()
392 xilinx_pm_request(PM_CLOCK_GETSTATE, clk_id, 0, 0, 0, ret_payload); in versal_clock_get_pll_rate()
395 printf("0%x PLL not enabled\n", clk_id); in versal_clock_get_pll_rate()
399 parent_id = clock[clock[id].parent[0].id].clk_id; in versal_clock_get_pll_rate()
402 xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload); in versal_clock_get_pll_rate()
404 xilinx_pm_request(PM_CLOCK_PLL_GETPARAM, clk_id, 2, 0, 0, ret_payload); in versal_clock_get_pll_rate()
412 static u32 versal_clock_mux(u32 clk_id) in versal_clock_mux() argument
415 u32 id = clk_id & 0xFFF; in versal_clock_mux()
424 static u32 versal_clock_get_parentid(u32 clk_id) in versal_clock_get_parentid() argument
428 u32 id = clk_id & 0xFFF; in versal_clock_get_parentid()
430 if (versal_clock_mux(clk_id)) { in versal_clock_get_parentid()
431 xilinx_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, in versal_clock_get_parentid()
436 debug("parent_id:0x%x\n", clock[clock[id].parent[parent_id].id].clk_id); in versal_clock_get_parentid()
437 return clock[clock[id].parent[parent_id].id].clk_id; in versal_clock_get_parentid()
440 static u32 versal_clock_gate(u32 clk_id) in versal_clock_gate() argument
442 u32 id = clk_id & 0xFFF; in versal_clock_gate()
452 static u32 versal_clock_div(u32 clk_id) in versal_clock_div() argument
455 u32 id = clk_id & 0xFFF; in versal_clock_div()
464 static u32 versal_clock_pll(u32 clk_id, u64 *clk_rate) in versal_clock_pll() argument
466 if (((clk_id >> NODE_SUBCLASS_SHIFT) & NODE_CLASS_MASK) == in versal_clock_pll()
468 ((clk_id >> NODE_CLASS_SHIFT) & NODE_CLASS_MASK) == in versal_clock_pll()
470 *clk_rate = versal_clock_get_pll_rate(clk_id); in versal_clock_pll()
477 static u64 versal_clock_calc(u32 clk_id) in versal_clock_calc() argument
483 if (versal_clock_pll(clk_id, &clk_rate)) in versal_clock_calc()
486 parent_id = versal_clock_get_parentid(clk_id); in versal_clock_calc()
489 return versal_clock_ref(clk_id); in versal_clock_calc()
496 if (versal_clock_div(clk_id)) { in versal_clock_calc()
497 div = versal_clock_get_div(clk_id); in versal_clock_calc()
504 static int versal_clock_get_rate(u32 clk_id, u64 *clk_rate) in versal_clock_get_rate() argument
506 if (((clk_id >> NODE_SUBCLASS_SHIFT) & in versal_clock_get_rate()
508 *clk_rate = versal_clock_ref(clk_id); in versal_clock_get_rate()
510 if (versal_clock_pll(clk_id, clk_rate)) in versal_clock_get_rate()
513 if (((clk_id >> NODE_SUBCLASS_SHIFT) & in versal_clock_get_rate()
515 ((clk_id >> NODE_CLASS_SHIFT) & in versal_clock_get_rate()
517 if (!versal_clock_gate(clk_id) && !versal_clock_mux(clk_id)) in versal_clock_get_rate()
519 *clk_rate = versal_clock_calc(clk_id); in versal_clock_get_rate()
540 ret = versal_clock_get_rate(clock[i].clk_id, &clk_rate); in soc_clk_dump()
573 clock[i].clk_id = (class << NODE_CLASS_SHIFT) | in versal_get_clock_info()
578 ret = versal_pm_clock_get_name(clock[i].clk_id, in versal_get_clock_info()
584 clock[i].type, clock[i].clk_id); in versal_get_clock_info()
671 u32 clk_id; in versal_clk_get_rate() local
676 clk_id = priv->clk[id].clk_id; in versal_clk_get_rate()
678 versal_clock_get_rate(clk_id, &clk_rate); in versal_clk_get_rate()
687 u32 clk_id; in versal_clk_set_rate() local
694 clk_id = priv->clk[id].clk_id; in versal_clk_set_rate()
696 ret = versal_clock_get_rate(clk_id, &clk_rate); in versal_clk_set_rate()
698 printf("Clock is not a Gate:0x%x\n", clk_id); in versal_clk_set_rate()
703 if (versal_clock_div(clk_id)) { in versal_clk_set_rate()
704 div = versal_clock_get_div(clk_id); in versal_clk_set_rate()
707 versal_clock_set_div(clk_id, div); in versal_clk_set_rate()
712 clk_id = versal_clock_get_parentid(clk_id); in versal_clk_set_rate()
713 } while (((clk_id >> NODE_SUBCLASS_SHIFT) & in versal_clk_set_rate()
716 printf("Clock didn't has Divisors:0x%x\n", priv->clk[id].clk_id); in versal_clk_set_rate()
724 u32 clk_id; in versal_clk_enable() local
726 clk_id = priv->clk[clk->id].clk_id; in versal_clk_enable()
728 return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL); in versal_clk_enable()