Lines Matching refs:pll
168 rockchip_get_pll_settings(struct rockchip_pll_clock *pll, ulong rate) in rockchip_get_pll_settings() argument
170 struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_get_pll_settings()
183 static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll, in rk3036_pll_set_rate() argument
189 rate = rockchip_get_pll_settings(pll, drate); in rk3036_pll_set_rate()
204 rk_clrsetreg(base + pll->mode_offset, in rk3036_pll_set_rate()
205 pll->mode_mask << pll->mode_shift, in rk3036_pll_set_rate()
206 RKCLK_PLL_MODE_SLOW << pll->mode_shift); in rk3036_pll_set_rate()
209 rk_setreg(base + pll->con_offset + 0x4, in rk3036_pll_set_rate()
212 rk_clrsetreg(base + pll->con_offset, in rk3036_pll_set_rate()
217 rk_clrsetreg(base + pll->con_offset + 0x4, in rk3036_pll_set_rate()
223 rk_clrsetreg(base + pll->con_offset + 0x4, in rk3036_pll_set_rate()
226 writel((readl(base + pll->con_offset + 0x8) & in rk3036_pll_set_rate()
229 base + pll->con_offset + 0x8); in rk3036_pll_set_rate()
233 rk_clrreg(base + pll->con_offset + 0x4, in rk3036_pll_set_rate()
237 while (!(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift))) in rk3036_pll_set_rate()
240 rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift, in rk3036_pll_set_rate()
241 RKCLK_PLL_MODE_NORMAL << pll->mode_shift); in rk3036_pll_set_rate()
243 pll, readl(base + pll->con_offset), in rk3036_pll_set_rate()
244 readl(base + pll->con_offset + 0x4), in rk3036_pll_set_rate()
245 readl(base + pll->con_offset + 0x8), in rk3036_pll_set_rate()
246 readl(base + pll->mode_offset)); in rk3036_pll_set_rate()
251 static ulong rk3036_pll_get_rate(struct rockchip_pll_clock *pll, in rk3036_pll_get_rate() argument
258 con = readl(base + pll->mode_offset); in rk3036_pll_get_rate()
259 shift = pll->mode_shift; in rk3036_pll_get_rate()
260 mask = pll->mode_mask << shift; in rk3036_pll_get_rate()
267 con = readl(base + pll->con_offset); in rk3036_pll_get_rate()
272 con = readl(base + pll->con_offset + 0x4); in rk3036_pll_get_rate()
279 con = readl(base + pll->con_offset + 0x8); in rk3036_pll_get_rate()
299 ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll, in rockchip_pll_get_rate() argument
305 switch (pll->type) { in rockchip_pll_get_rate()
307 pll->mode_mask = PLL_MODE_MASK; in rockchip_pll_get_rate()
308 rate = rk3036_pll_get_rate(pll, base, pll_id); in rockchip_pll_get_rate()
311 pll->mode_mask = PLL_RK3328_MODE_MASK; in rockchip_pll_get_rate()
312 rate = rk3036_pll_get_rate(pll, base, pll_id); in rockchip_pll_get_rate()
321 int rockchip_pll_set_rate(struct rockchip_pll_clock *pll, in rockchip_pll_set_rate() argument
327 if (rockchip_pll_get_rate(pll, base, pll_id) == drate) in rockchip_pll_set_rate()
330 switch (pll->type) { in rockchip_pll_set_rate()
332 pll->mode_mask = PLL_MODE_MASK; in rockchip_pll_set_rate()
333 ret = rk3036_pll_set_rate(pll, base, pll_id, drate); in rockchip_pll_set_rate()
336 pll->mode_mask = PLL_RK3328_MODE_MASK; in rockchip_pll_set_rate()
337 ret = rk3036_pll_set_rate(pll, base, pll_id, drate); in rockchip_pll_set_rate()