Lines Matching refs:con
265 u32 con, shift, mask; in rkclk_pll_get_rate() local
267 con = readl(mode); in rkclk_pll_get_rate()
271 switch ((con & mask) >> shift) { in rkclk_pll_get_rate()
276 con = readl(&pll->con0); in rkclk_pll_get_rate()
277 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; in rkclk_pll_get_rate()
278 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; in rkclk_pll_get_rate()
279 con = readl(&pll->con1); in rkclk_pll_get_rate()
280 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; in rkclk_pll_get_rate()
281 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; in rkclk_pll_get_rate()
292 u32 div, con; in px30_i2c_get_clk() local
296 con = readl(&cru->clksel_con[49]); in px30_i2c_get_clk()
297 div = con >> CLK_I2C0_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; in px30_i2c_get_clk()
300 con = readl(&cru->clksel_con[49]); in px30_i2c_get_clk()
301 div = con >> CLK_I2C1_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; in px30_i2c_get_clk()
304 con = readl(&cru->clksel_con[50]); in px30_i2c_get_clk()
305 div = con >> CLK_I2C2_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; in px30_i2c_get_clk()
308 con = readl(&cru->clksel_con[50]); in px30_i2c_get_clk()
309 div = con >> CLK_I2C3_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; in px30_i2c_get_clk()
422 u32 con, fracdiv, gate; in px30_i2s_get_clk() local
429 con = readl(&cru->clksel_con[30]); in px30_i2s_get_clk()
437 con, gate, fracdiv); in px30_i2s_get_clk()
483 u32 div, con; in px30_nandc_get_clk() local
485 con = readl(&cru->clksel_con[15]); in px30_nandc_get_clk()
486 div = (con & NANDC_DIV_MASK) >> NANDC_DIV_SHIFT; in px30_nandc_get_clk()
515 u32 div, con, con_id; in px30_mmc_get_clk() local
531 con = readl(&cru->clksel_con[con_id]); in px30_mmc_get_clk()
532 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; in px30_mmc_get_clk()
534 if ((con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT in px30_mmc_get_clk()
587 u32 div, con; in px30_pwm_get_clk() local
591 con = readl(&cru->clksel_con[52]); in px30_pwm_get_clk()
592 div = con >> CLK_PWM0_DIV_CON_SHIFT & CLK_PWM_DIV_CON_MASK; in px30_pwm_get_clk()
595 con = readl(&cru->clksel_con[52]); in px30_pwm_get_clk()
596 div = con >> CLK_PWM1_DIV_CON_SHIFT & CLK_PWM_DIV_CON_MASK; in px30_pwm_get_clk()
640 u32 div, con; in px30_saradc_get_clk() local
642 con = readl(&cru->clksel_con[55]); in px30_saradc_get_clk()
643 div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK; in px30_saradc_get_clk()
666 u32 div, con; in px30_tsadc_get_clk() local
668 con = readl(&cru->clksel_con[54]); in px30_tsadc_get_clk()
669 div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK; in px30_tsadc_get_clk()
692 u32 div, con; in px30_spi_get_clk() local
696 con = readl(&cru->clksel_con[53]); in px30_spi_get_clk()
697 div = con >> CLK_SPI0_DIV_CON_SHIFT & CLK_SPI_DIV_CON_MASK; in px30_spi_get_clk()
700 con = readl(&cru->clksel_con[53]); in px30_spi_get_clk()
701 div = con >> CLK_SPI1_DIV_CON_SHIFT & CLK_SPI_DIV_CON_MASK; in px30_spi_get_clk()
745 u32 div, con, parent; in px30_vop_get_clk() local
750 con = readl(&cru->clksel_con[3]); in px30_vop_get_clk()
751 div = con & ACLK_VO_DIV_MASK; in px30_vop_get_clk()
755 con = readl(&cru->clksel_con[5]); in px30_vop_get_clk()
756 div = con & DCLK_VOPB_DIV_MASK; in px30_vop_get_clk()
760 con = readl(&cru->clksel_con[8]); in px30_vop_get_clk()
761 div = con & DCLK_VOPL_DIV_MASK; in px30_vop_get_clk()
842 u32 div, con, parent; in px30_bus_get_clk() local
846 con = readl(&cru->clksel_con[23]); in px30_bus_get_clk()
847 div = (con & BUS_ACLK_DIV_MASK) >> BUS_ACLK_DIV_SHIFT; in px30_bus_get_clk()
851 con = readl(&cru->clksel_con[24]); in px30_bus_get_clk()
852 div = (con & BUS_HCLK_DIV_MASK) >> BUS_HCLK_DIV_SHIFT; in px30_bus_get_clk()
858 con = readl(&cru->clksel_con[24]); in px30_bus_get_clk()
859 div = (con & BUS_PCLK_DIV_MASK) >> BUS_PCLK_DIV_SHIFT; in px30_bus_get_clk()
914 u32 div, con, parent; in px30_peri_get_clk() local
918 con = readl(&cru->clksel_con[14]); in px30_peri_get_clk()
919 div = (con & PERI_ACLK_DIV_MASK) >> PERI_ACLK_DIV_SHIFT; in px30_peri_get_clk()
923 con = readl(&cru->clksel_con[14]); in px30_peri_get_clk()
924 div = (con & PERI_HCLK_DIV_MASK) >> PERI_HCLK_DIV_SHIFT; in px30_peri_get_clk()
972 u32 div, con, parent; in px30_crypto_get_clk() local
976 con = readl(&cru->clksel_con[25]); in px30_crypto_get_clk()
977 div = (con & CRYPTO_DIV_MASK) >> CRYPTO_DIV_SHIFT; in px30_crypto_get_clk()
981 con = readl(&cru->clksel_con[25]); in px30_crypto_get_clk()
982 div = (con & CRYPTO_APK_DIV_MASK) >> CRYPTO_APK_DIV_SHIFT; in px30_crypto_get_clk()
1029 u32 con; in px30_i2s1_mclk_get_clk() local
1031 con = readl(&cru->clksel_con[30]); in px30_i2s1_mclk_get_clk()
1033 if (!(con & CLK_I2S1_OUT_SEL_MASK)) in px30_i2s1_mclk_get_clk()
1060 u32 con = readl(&cru->clksel_con[22]); in px30_mac_set_clk() local
1064 if ((con >> GMAC_PLL_SEL_SHIFT) & GMAC_PLL_SEL_CPLL) in px30_mac_set_clk()
1066 else if ((con >> GMAC_PLL_SEL_SHIFT) & GMAC_PLL_SEL_NPLL) in px30_mac_set_clk()
1495 u32 div, con; in px30_pclk_pmu_get_pmuclk() local
1497 con = readl(&pmucru->pmu_clksel_con[0]); in px30_pclk_pmu_get_pmuclk()
1498 div = (con & CLK_PMU_PCLK_DIV_MASK) >> CLK_PMU_PCLK_DIV_SHIFT; in px30_pclk_pmu_get_pmuclk()