Lines Matching refs:rk_clrsetreg
233 rk_clrsetreg(mode, pll_mode_mask[pll_id], in rkclk_set_pll()
241 rk_clrsetreg(&pll->con0, in rkclk_set_pll()
244 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkclk_set_pll()
255 rk_clrsetreg(mode, pll_mode_mask[pll_id], in rkclk_set_pll()
329 rk_clrsetreg(&cru->clksel_con[49], in px30_i2c_set_clk()
336 rk_clrsetreg(&cru->clksel_con[49], in px30_i2c_set_clk()
343 rk_clrsetreg(&cru->clksel_con[50], in px30_i2c_set_clk()
350 rk_clrsetreg(&cru->clksel_con[50], in px30_i2c_set_clk()
460 rk_clrsetreg(&cru->clksel_con[30], in px30_i2s_set_clk()
462 rk_clrsetreg(&cru->clksel_con[30], in px30_i2s_set_clk()
464 rk_clrsetreg(&cru->clksel_con[30], in px30_i2s_set_clk()
468 rk_clrsetreg(&cru->clkgate_con[10], in px30_i2s_set_clk()
502 rk_clrsetreg(&cru->clksel_con[15], in px30_nandc_set_clk()
568 rk_clrsetreg(&cru->clksel_con[con_id], in px30_mmc_set_clk()
573 rk_clrsetreg(&cru->clksel_con[con_id], in px30_mmc_set_clk()
578 rk_clrsetreg(&cru->clksel_con[con_id + 1], EMMC_CLK_SEL_MASK, in px30_mmc_set_clk()
616 rk_clrsetreg(&cru->clksel_con[52], in px30_pwm_set_clk()
623 rk_clrsetreg(&cru->clksel_con[52], in px30_pwm_set_clk()
656 rk_clrsetreg(&cru->clksel_con[55], in px30_saradc_set_clk()
682 rk_clrsetreg(&cru->clksel_con[54], in px30_tsadc_set_clk()
721 rk_clrsetreg(&cru->clksel_con[53], in px30_spi_set_clk()
728 rk_clrsetreg(&cru->clksel_con[53], in px30_spi_set_clk()
782 rk_clrsetreg(&cru->clksel_con[3], in px30_vop_set_clk()
798 rk_clrsetreg(&cru->clksel_con[5], in px30_vop_set_clk()
824 rk_clrsetreg(&cru->clksel_con[8], in px30_vop_set_clk()
882 rk_clrsetreg(&cru->clksel_con[23], in px30_bus_set_clk()
890 rk_clrsetreg(&cru->clksel_con[24], in px30_bus_set_clk()
899 rk_clrsetreg(&cru->clksel_con[24], in px30_bus_set_clk()
949 rk_clrsetreg(&cru->clksel_con[14], in px30_peri_set_clk()
955 rk_clrsetreg(&cru->clksel_con[14], in px30_peri_set_clk()
1007 rk_clrsetreg(&cru->clksel_con[25], in px30_crypto_set_clk()
1013 rk_clrsetreg(&cru->clksel_con[25], in px30_crypto_set_clk()
1049 rk_clrsetreg(&cru->clksel_con[30], CLK_I2S1_OUT_SEL_MASK, in px30_i2s1_mclk_set_clk()
1051 rk_clrsetreg(&cru->clkgate_con[10], CLK_I2S1_OUT_MCLK_PAD_MASK, in px30_i2s1_mclk_set_clk()
1077 rk_clrsetreg(&cru->clksel_con[22], CLK_GMAC_DIV_MASK, in px30_mac_set_clk()
1092 rk_clrsetreg(&cru->clksel_con[23], RMII_CLK_SEL_MASK, in px30_mac_set_speed_clk()
1139 rk_clrsetreg(&cru->clksel_con[0], in px30_armclk_set_clk()
1147 rk_clrsetreg(&cru->clksel_con[0], in px30_armclk_set_clk()
1346 rk_clrsetreg(&cru->clksel_con[23], RMII_EXTCLK_SEL_MASK, in px30_gmac_set_parent()
1350 rk_clrsetreg(&cru->clksel_con[23], RMII_EXTCLK_SEL_MASK, in px30_gmac_set_parent()
1511 rk_clrsetreg(&pmucru->pmu_clksel_con[0], in px30_pclk_pmu_set_pmuclk()