Lines Matching refs:con
234 uint32_t con; in rkclk_pll_get_rate() local
243 con = readl(&cru->cru_mode_con); in rkclk_pll_get_rate()
245 switch ((con >> shift) & APLL_MODE_MASK) { in rkclk_pll_get_rate()
250 con = readl(&pll->con0); in rkclk_pll_get_rate()
251 no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1; in rkclk_pll_get_rate()
252 nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1; in rkclk_pll_get_rate()
253 con = readl(&pll->con1); in rkclk_pll_get_rate()
254 nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1; in rkclk_pll_get_rate()
267 u32 con; in rockchip_mmc_get_clk() local
272 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
273 div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK; in rockchip_mmc_get_clk()
277 con = readl(&cru->cru_clksel_con[11]); in rockchip_mmc_get_clk()
278 div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK; in rockchip_mmc_get_clk()
282 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
283 div = (con >> SDIO_DIV_SHIFT) & SDIO_DIV_MASK; in rockchip_mmc_get_clk()
332 u32 con; in rockchip_spi_get_clk() local
336 con = readl(&cru->cru_clksel_con[25]); in rockchip_spi_get_clk()
337 div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK; in rockchip_spi_get_clk()
340 con = readl(&cru->cru_clksel_con[25]); in rockchip_spi_get_clk()
341 div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK; in rockchip_spi_get_clk()