Lines Matching refs:rk_clrsetreg
68 rk_clrsetreg(&pll->con0, in rkclk_set_pll()
71 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkclk_set_pll()
92 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
112 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
117 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
135 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
140 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
160 rk_clrsetreg(&cru->cru_clksel_con[10], in rkclk_init()
169 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
270 rk_clrsetreg(&cru->cru_clksel_con[5], CLK_MAC_DIV_MASK, in rk322x_mac_set_clk()
304 rk_clrsetreg(&cru->cru_clksel_con[11], in rockchip_mmc_set_clk()
307 rk_clrsetreg(&cru->cru_clksel_con[12], in rockchip_mmc_set_clk()
313 rk_clrsetreg(&cru->cru_clksel_con[11], in rockchip_mmc_set_clk()
346 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rk322x_ddr_set_clk()
350 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rk322x_ddr_set_clk()
418 rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), 0); in rk322x_gmac_set_parent()
428 rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), BIT(5)); in rk322x_gmac_set_parent()
449 rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), 0); in rk322x_gmac_extclk_set_parent()
453 rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), BIT(10)); in rk322x_gmac_extclk_set_parent()