Lines Matching refs:con
317 u32 con = readl(&cru->cru_clksel_con[21]); in rockchip_mac_set_clk() local
321 if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) == in rockchip_mac_set_clk()
324 else if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) == in rockchip_mac_set_clk()
548 uint32_t con; in rkclk_pll_get_rate() local
557 con = readl(&cru->cru_mode_con); in rkclk_pll_get_rate()
559 switch ((con >> shift) & CRU_MODE_MASK) { in rkclk_pll_get_rate()
564 con = readl(&pll->con0); in rkclk_pll_get_rate()
565 no = ((con & CLKOD_MASK) >> CLKOD_SHIFT) + 1; in rkclk_pll_get_rate()
566 nr = ((con & CLKR_MASK) >> CLKR_SHIFT) + 1; in rkclk_pll_get_rate()
567 con = readl(&pll->con1); in rkclk_pll_get_rate()
568 nf = ((con & CLKF_MASK) >> CLKF_SHIFT) + 1; in rkclk_pll_get_rate()
582 u32 con; in rockchip_mmc_get_clk() local
587 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
588 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT; in rockchip_mmc_get_clk()
589 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; in rockchip_mmc_get_clk()
593 con = readl(&cru->cru_clksel_con[11]); in rockchip_mmc_get_clk()
594 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT; in rockchip_mmc_get_clk()
595 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT; in rockchip_mmc_get_clk()
599 con = readl(&cru->cru_clksel_con[12]); in rockchip_mmc_get_clk()
600 mux = (con & SDIO0_PLL_MASK) >> SDIO0_PLL_SHIFT; in rockchip_mmc_get_clk()
601 div = (con & SDIO0_DIV_MASK) >> SDIO0_DIV_SHIFT; in rockchip_mmc_get_clk()
665 u32 con; in rockchip_spi_get_clk() local
669 con = readl(&cru->cru_clksel_con[25]); in rockchip_spi_get_clk()
670 mux = (con & SPI0_PLL_MASK) >> SPI0_PLL_SHIFT; in rockchip_spi_get_clk()
671 div = (con & SPI0_DIV_MASK) >> SPI0_DIV_SHIFT; in rockchip_spi_get_clk()
674 con = readl(&cru->cru_clksel_con[25]); in rockchip_spi_get_clk()
675 mux = (con & SPI1_PLL_MASK) >> SPI1_PLL_SHIFT; in rockchip_spi_get_clk()
676 div = (con & SPI1_DIV_MASK) >> SPI1_DIV_SHIFT; in rockchip_spi_get_clk()
679 con = readl(&cru->cru_clksel_con[39]); in rockchip_spi_get_clk()
680 mux = (con & SPI2_PLL_MASK) >> SPI2_PLL_SHIFT; in rockchip_spi_get_clk()
681 div = (con & SPI2_DIV_MASK) >> SPI2_DIV_SHIFT; in rockchip_spi_get_clk()