Lines Matching refs:rk_clrsetreg
261 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_SLOW << mode_shift); in rkclk_set_pll()
264 rk_clrsetreg(&pll_con[1], PLL_DSMPD_MASK, in rkclk_set_pll()
267 rk_clrsetreg(&pll_con[0], in rkclk_set_pll()
271 rk_clrsetreg(&pll_con[1], in rkclk_set_pll()
281 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift); in rkclk_set_pll()
301 rk_clrsetreg(&cru->clksel_con[28], in rkclk_init()
305 rk_clrsetreg(&cru->clksel_con[29], in rkclk_init()
324 rk_clrsetreg(&cru->clksel_con[0], in rk3328_configure_cpu()
329 rk_clrsetreg(&cru->clksel_con[1], in rk3328_configure_cpu()
374 rk_clrsetreg(&cru->clksel_con[34], in rk3328_i2c_set_clk()
381 rk_clrsetreg(&cru->clksel_con[34], in rk3328_i2c_set_clk()
388 rk_clrsetreg(&cru->clksel_con[35], in rk3328_i2c_set_clk()
395 rk_clrsetreg(&cru->clksel_con[35], in rk3328_i2c_set_clk()
436 rk_clrsetreg(&cru->clksel_con[27], GMAC2IO_CLK_DIV_MASK, in rk3328_gmac2io_set_clk()
498 rk_clrsetreg(&cru->clksel_con[con_id], in rk3328_mmc_set_clk()
503 rk_clrsetreg(&cru->clksel_con[con_id], in rk3328_mmc_set_clk()
526 rk_clrsetreg(&cru->clksel_con[24], in rk3328_pwm_set_clk()
552 rk_clrsetreg(&cru->clksel_con[23], in rk3328_saradc_set_clk()
576 rk_clrsetreg(&cru->clksel_con[24], in rk3328_spi_set_clk()