Lines Matching refs:CLK_GENERAL
59 case CLK_GENERAL: in rv1108_pll_id()
156 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_mac_set_clk()
181 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_sfc_set_clk()
312 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_aclk_bus_get_clk()
324 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_aclk_bus_set_clk()
340 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_aclk_peri_get_clk()
352 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_hclk_peri_get_clk()
364 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_pclk_peri_get_clk()
376 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_aclk_peri_set_clk()
392 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_hclk_peri_set_clk()
407 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_pclk_peri_set_clk()
517 div = DIV_ROUND_UP(rkclk_pll_get_rate(cru, CLK_GENERAL), rate); in rv1108_mmc_set_clk()
523 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_mmc_set_clk()
649 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); in rkclk_init()
657 gpll = rkclk_pll_get_rate(cru, CLK_GENERAL); in rkclk_init()