Lines Matching refs:ddr
150 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr, in set_csn_config() argument
227 ddr->cs[i].config = (0 in set_csn_config()
246 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config); in set_csn_config()
251 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr) in set_csn_config_2() argument
255 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24); in set_csn_config_2()
256 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2); in set_csn_config_2()
297 fsl_ddr_cfg_regs_t *ddr, in set_timing_cfg_0() argument
440 ddr->timing_cfg_0 = (0 in set_timing_cfg_0()
450 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); in set_timing_cfg_0()
456 fsl_ddr_cfg_regs_t *ddr, in set_timing_cfg_3() argument
493 ddr->timing_cfg_3 = (0 in set_timing_cfg_3()
503 debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3); in set_timing_cfg_3()
508 fsl_ddr_cfg_regs_t *ddr, in set_timing_cfg_1() argument
621 ddr->timing_cfg_1 = (0 in set_timing_cfg_1()
631 debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1); in set_timing_cfg_1()
636 fsl_ddr_cfg_regs_t *ddr, in set_timing_cfg_2() argument
714 ddr->timing_cfg_2 = (0 in set_timing_cfg_2()
724 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2); in set_timing_cfg_2()
729 fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_rcw() argument
739 ddr->ddr_sdram_rcw_1 = popts->rcw_1; in set_ddr_sdram_rcw()
740 ddr->ddr_sdram_rcw_2 = popts->rcw_2; in set_ddr_sdram_rcw()
741 ddr->ddr_sdram_rcw_3 = popts->rcw_3; in set_ddr_sdram_rcw()
753 ddr->ddr_sdram_rcw_1 = in set_ddr_sdram_rcw()
762 ddr->ddr_sdram_rcw_2 = in set_ddr_sdram_rcw()
771 ddr->ddr_sdram_rcw_3 = in set_ddr_sdram_rcw()
775 ddr->ddr_sdram_rcw_1); in set_ddr_sdram_rcw()
777 ddr->ddr_sdram_rcw_2); in set_ddr_sdram_rcw()
779 ddr->ddr_sdram_rcw_3); in set_ddr_sdram_rcw()
784 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_cfg() argument
850 ddr->ddr_sdram_cfg = (0 in set_ddr_sdram_cfg()
870 debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg); in set_ddr_sdram_cfg()
875 fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_cfg_2() argument
941 ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE; in set_ddr_sdram_cfg_2()
942 debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init); in set_ddr_sdram_cfg_2()
952 ddr->ddr_sdram_cfg_2 = (0 in set_ddr_sdram_cfg_2()
971 debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2); in set_ddr_sdram_cfg_2()
977 fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_mode_2() argument
1018 ddr->ddr_sdram_mode_2 = (0 in set_ddr_sdram_mode_2()
1022 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); in set_ddr_sdram_mode_2()
1035 ddr->ddr_sdram_mode_4 = (0 in set_ddr_sdram_mode_2()
1041 ddr->ddr_sdram_mode_6 = (0 in set_ddr_sdram_mode_2()
1047 ddr->ddr_sdram_mode_8 = (0 in set_ddr_sdram_mode_2()
1055 ddr->ddr_sdram_mode_4); in set_ddr_sdram_mode_2()
1057 ddr->ddr_sdram_mode_6); in set_ddr_sdram_mode_2()
1059 ddr->ddr_sdram_mode_8); in set_ddr_sdram_mode_2()
1065 fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_mode_2() argument
1093 ddr->ddr_sdram_mode_2 = (0 in set_ddr_sdram_mode_2()
1097 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); in set_ddr_sdram_mode_2()
1110 ddr->ddr_sdram_mode_4 = (0 in set_ddr_sdram_mode_2()
1116 ddr->ddr_sdram_mode_6 = (0 in set_ddr_sdram_mode_2()
1122 ddr->ddr_sdram_mode_8 = (0 in set_ddr_sdram_mode_2()
1130 ddr->ddr_sdram_mode_4); in set_ddr_sdram_mode_2()
1132 ddr->ddr_sdram_mode_6); in set_ddr_sdram_mode_2()
1134 ddr->ddr_sdram_mode_8); in set_ddr_sdram_mode_2()
1141 fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_mode_2() argument
1149 ddr->ddr_sdram_mode_2 = (0 in set_ddr_sdram_mode_2()
1153 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); in set_ddr_sdram_mode_2()
1159 static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_mode_9() argument
1172 if ((ddr->cs[0].config & SDRAM_CS_CONFIG_EN) && in set_ddr_sdram_mode_9()
1173 (ddr->cs[1].config & SDRAM_CS_CONFIG_EN) && in set_ddr_sdram_mode_9()
1174 (ddr->cs[2].config & SDRAM_CS_CONFIG_EN) && in set_ddr_sdram_mode_9()
1175 (ddr->cs[3].config & SDRAM_CS_CONFIG_EN)) in set_ddr_sdram_mode_9()
1178 if (ddr->cs[0].config & SDRAM_CS_CONFIG_EN) { in set_ddr_sdram_mode_9()
1190 if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) && in set_ddr_sdram_mode_9()
1204 ddr->ddr_sdram_mode_9 = (0 in set_ddr_sdram_mode_9()
1214 debug("FSLDDR: ddr_sdram_mode_9 = 0x%08x\n", ddr->ddr_sdram_mode_9); in set_ddr_sdram_mode_9()
1218 (ddr->cs[i].config & SDRAM_CS_CONFIG_EN)) { in set_ddr_sdram_mode_9()
1225 if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) && in set_ddr_sdram_mode_9()
1242 ddr->ddr_sdram_mode_11 = (0 in set_ddr_sdram_mode_9()
1248 ddr->ddr_sdram_mode_13 = (0 in set_ddr_sdram_mode_9()
1254 ddr->ddr_sdram_mode_15 = (0 in set_ddr_sdram_mode_9()
1262 ddr->ddr_sdram_mode_11); in set_ddr_sdram_mode_9()
1264 ddr->ddr_sdram_mode_13); in set_ddr_sdram_mode_9()
1266 ddr->ddr_sdram_mode_15); in set_ddr_sdram_mode_9()
1272 fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_mode_10() argument
1287 ddr->ddr_sdram_mode_10 = (0 in set_ddr_sdram_mode_10()
1291 debug("FSLDDR: ddr_sdram_mode_10 = 0x%08x\n", ddr->ddr_sdram_mode_10); in set_ddr_sdram_mode_10()
1296 ddr->ddr_sdram_mode_12 = (0 in set_ddr_sdram_mode_10()
1302 ddr->ddr_sdram_mode_14 = (0 in set_ddr_sdram_mode_10()
1308 ddr->ddr_sdram_mode_16 = (0 in set_ddr_sdram_mode_10()
1316 ddr->ddr_sdram_mode_12); in set_ddr_sdram_mode_10()
1318 ddr->ddr_sdram_mode_14); in set_ddr_sdram_mode_10()
1320 ddr->ddr_sdram_mode_16); in set_ddr_sdram_mode_10()
1328 fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_interval() argument
1340 ddr->ddr_sdram_interval = (0 in set_ddr_sdram_interval()
1344 debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval); in set_ddr_sdram_interval()
1350 fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_mode() argument
1472 ddr->ddr_sdram_mode = (0 in set_ddr_sdram_mode()
1477 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); in set_ddr_sdram_mode()
1490 ddr->ddr_sdram_mode_3 = (0 in set_ddr_sdram_mode()
1496 ddr->ddr_sdram_mode_5 = (0 in set_ddr_sdram_mode()
1502 ddr->ddr_sdram_mode_7 = (0 in set_ddr_sdram_mode()
1510 ddr->ddr_sdram_mode_3); in set_ddr_sdram_mode()
1512 ddr->ddr_sdram_mode_5); in set_ddr_sdram_mode()
1514 ddr->ddr_sdram_mode_5); in set_ddr_sdram_mode()
1521 fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_mode() argument
1663 ddr->ddr_sdram_mode = (0 in set_ddr_sdram_mode()
1668 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); in set_ddr_sdram_mode()
1685 ddr->ddr_sdram_mode_3 = (0 in set_ddr_sdram_mode()
1691 ddr->ddr_sdram_mode_5 = (0 in set_ddr_sdram_mode()
1697 ddr->ddr_sdram_mode_7 = (0 in set_ddr_sdram_mode()
1705 ddr->ddr_sdram_mode_3); in set_ddr_sdram_mode()
1707 ddr->ddr_sdram_mode_5); in set_ddr_sdram_mode()
1709 ddr->ddr_sdram_mode_5); in set_ddr_sdram_mode()
1717 fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_mode() argument
1837 ddr->ddr_sdram_mode = (0 in set_ddr_sdram_mode()
1841 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); in set_ddr_sdram_mode()
1846 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr) in set_ddr_data_init() argument
1855 ddr->ddr_data_init = init_value; in set_ddr_data_init()
1863 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_clk_cntl() argument
1881 ddr->ddr_sdram_clk_cntl = (0 in set_ddr_sdram_clk_cntl()
1885 debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl); in set_ddr_sdram_clk_cntl()
1889 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr) in set_ddr_init_addr() argument
1893 ddr->ddr_init_addr = init_addr; in set_ddr_init_addr()
1897 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr) in set_ddr_init_ext_addr() argument
1902 ddr->ddr_init_ext_addr = (0 in set_ddr_init_ext_addr()
1909 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr, in set_timing_cfg_4() argument
1939 ddr->timing_cfg_4 = (0 in set_timing_cfg_4()
1947 debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4); in set_timing_cfg_4()
1951 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency) in set_timing_cfg_5() argument
1959 unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) + in set_timing_cfg_5()
1960 ((ddr->timing_cfg_2 & 0x00040000) >> 14); in set_timing_cfg_5()
1969 ddr->timing_cfg_5 = (0 in set_timing_cfg_5()
1975 debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5); in set_timing_cfg_5()
1979 static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr) in set_timing_cfg_6() argument
1987 ddr->timing_cfg_6 = (0 in set_timing_cfg_6()
1994 debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6); in set_timing_cfg_6()
1998 fsl_ddr_cfg_regs_t *ddr, in set_timing_cfg_7() argument
2010 if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN && in set_timing_cfg_7()
2013 par_lat = (ddr->ddr_sdram_rcw_2 & 0xf) + 1; in set_timing_cfg_7()
2038 ddr->timing_cfg_7 = (0 in set_timing_cfg_7()
2045 debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7); in set_timing_cfg_7()
2049 fsl_ddr_cfg_regs_t *ddr, in set_timing_cfg_8() argument
2057 int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) + in set_timing_cfg_8()
2058 ((ddr->timing_cfg_2 & 0x00040000) >> 14); in set_timing_cfg_8()
2087 ddr->timing_cfg_8 = (0 in set_timing_cfg_8()
2097 debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8); in set_timing_cfg_8()
2101 fsl_ddr_cfg_regs_t *ddr, in set_timing_cfg_9() argument
2114 ddr->timing_cfg_9 = (refrec_cid_mclk & 0x3ff) << 16 | in set_timing_cfg_9()
2117 debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9); in set_timing_cfg_9()
2121 static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr, in set_ddr_dq_mapping() argument
2124 unsigned int acc_ecc_en = (ddr->ddr_sdram_cfg >> 2) & 0x1; in set_ddr_dq_mapping()
2136 ddr->dq_map_0 = ((dimm_params[i].dq_mapping[0] & 0x3F) << 26) | in set_ddr_dq_mapping()
2142 ddr->dq_map_1 = ((dimm_params[i].dq_mapping[5] & 0x3F) << 26) | in set_ddr_dq_mapping()
2148 ddr->dq_map_2 = ((dimm_params[i].dq_mapping[12] & 0x3F) << 26) | in set_ddr_dq_mapping()
2155 ddr->dq_map_3 = ((dimm_params[i].dq_mapping[17] & 0x3F) << 26) | in set_ddr_dq_mapping()
2161 debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0); in set_ddr_dq_mapping()
2162 debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1); in set_ddr_dq_mapping()
2163 debug("FSLDDR: dq_map_2 = 0x%08x\n", ddr->dq_map_2); in set_ddr_dq_mapping()
2164 debug("FSLDDR: dq_map_3 = 0x%08x\n", ddr->dq_map_3); in set_ddr_dq_mapping()
2166 static void set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr, in set_ddr_sdram_cfg_3() argument
2173 ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16; in set_ddr_sdram_cfg_3()
2175 ddr->ddr_sdram_cfg_3 |= popts->registered_dimm_en ? 1 : 0; in set_ddr_sdram_cfg_3()
2182 ddr->ddr_sdram_cfg_3 |= ((popts->package_3ds + 1) >> 1) in set_ddr_sdram_cfg_3()
2187 debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3); in set_ddr_sdram_cfg_3()
2192 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en) in set_ddr_zq_cntl() argument
2216 ddr->ddr_zq_cntl = (0 in set_ddr_zq_cntl()
2225 debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl); in set_ddr_zq_cntl()
2229 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en, in set_ddr_wrlvl_cntl() argument
2285 ddr->ddr_wrlvl_cntl = (0 in set_ddr_wrlvl_cntl()
2294 debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl); in set_ddr_wrlvl_cntl()
2295 ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2; in set_ddr_wrlvl_cntl()
2296 debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2); in set_ddr_wrlvl_cntl()
2297 ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3; in set_ddr_wrlvl_cntl()
2298 debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3); in set_ddr_wrlvl_cntl()
2303 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it) in set_ddr_sr_cntr() argument
2306 ddr->ddr_sr_cntr = (sr_it & 0xF) << 16; in set_ddr_sr_cntr()
2309 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) in set_ddr_eor() argument
2312 ddr->ddr_eor = 0x40000000; /* address hash enable */ in set_ddr_eor()
2317 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) in set_ddr_cdr1() argument
2319 ddr->ddr_cdr1 = popts->ddr_cdr1; in set_ddr_cdr1()
2320 debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1); in set_ddr_cdr1()
2323 static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) in set_ddr_cdr2() argument
2325 ddr->ddr_cdr2 = popts->ddr_cdr2; in set_ddr_cdr2()
2326 debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2); in set_ddr_cdr2()
2330 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) in check_fsl_memctl_config_regs() argument
2338 if (ddr->ddr_sdram_cfg & 0x10000000 in check_fsl_memctl_config_regs()
2339 && ddr->ddr_sdram_cfg & 0x00008000) { in check_fsl_memctl_config_regs()
2351 fsl_ddr_cfg_regs_t *ddr, in compute_fsl_memctl_config_regs() argument
2367 memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t)); in compute_fsl_memctl_config_regs()
2498 ddr->cs[i].bnds = (0 in compute_fsl_memctl_config_regs()
2504 ddr->cs[i].bnds = 0xffffffff; in compute_fsl_memctl_config_regs()
2507 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds); in compute_fsl_memctl_config_regs()
2508 set_csn_config(dimm_number, i, ddr, popts, dimm_params); in compute_fsl_memctl_config_regs()
2509 set_csn_config_2(i, ddr); in compute_fsl_memctl_config_regs()
2519 set_ddr_eor(ddr, popts); in compute_fsl_memctl_config_regs()
2522 set_timing_cfg_0(ctrl_num, ddr, popts, dimm_params); in compute_fsl_memctl_config_regs()
2525 set_timing_cfg_3(ctrl_num, ddr, popts, common_dimm, cas_latency, in compute_fsl_memctl_config_regs()
2527 set_timing_cfg_1(ctrl_num, ddr, popts, common_dimm, cas_latency); in compute_fsl_memctl_config_regs()
2528 set_timing_cfg_2(ctrl_num, ddr, popts, common_dimm, in compute_fsl_memctl_config_regs()
2531 set_ddr_cdr1(ddr, popts); in compute_fsl_memctl_config_regs()
2532 set_ddr_cdr2(ddr, popts); in compute_fsl_memctl_config_regs()
2533 set_ddr_sdram_cfg(ddr, popts, common_dimm); in compute_fsl_memctl_config_regs()
2539 ddr->debug[18] = popts->cswl_override; in compute_fsl_memctl_config_regs()
2541 set_ddr_sdram_cfg_2(ctrl_num, ddr, popts, unq_mrs_en); in compute_fsl_memctl_config_regs()
2542 set_ddr_sdram_mode(ctrl_num, ddr, popts, common_dimm, in compute_fsl_memctl_config_regs()
2544 set_ddr_sdram_mode_2(ctrl_num, ddr, popts, common_dimm, unq_mrs_en); in compute_fsl_memctl_config_regs()
2546 set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en); in compute_fsl_memctl_config_regs()
2547 set_ddr_sdram_mode_10(ctrl_num, ddr, popts, common_dimm, unq_mrs_en); in compute_fsl_memctl_config_regs()
2549 set_ddr_sdram_rcw(ctrl_num, ddr, popts, common_dimm); in compute_fsl_memctl_config_regs()
2551 set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm); in compute_fsl_memctl_config_regs()
2552 set_ddr_data_init(ddr); in compute_fsl_memctl_config_regs()
2553 set_ddr_sdram_clk_cntl(ddr, popts); in compute_fsl_memctl_config_regs()
2554 set_ddr_init_addr(ddr); in compute_fsl_memctl_config_regs()
2555 set_ddr_init_ext_addr(ddr); in compute_fsl_memctl_config_regs()
2556 set_timing_cfg_4(ddr, popts); in compute_fsl_memctl_config_regs()
2557 set_timing_cfg_5(ddr, cas_latency); in compute_fsl_memctl_config_regs()
2559 set_ddr_sdram_cfg_3(ddr, popts); in compute_fsl_memctl_config_regs()
2560 set_timing_cfg_6(ddr); in compute_fsl_memctl_config_regs()
2561 set_timing_cfg_7(ctrl_num, ddr, popts, common_dimm); in compute_fsl_memctl_config_regs()
2562 set_timing_cfg_8(ctrl_num, ddr, popts, common_dimm, cas_latency); in compute_fsl_memctl_config_regs()
2563 set_timing_cfg_9(ctrl_num, ddr, popts, common_dimm); in compute_fsl_memctl_config_regs()
2564 set_ddr_dq_mapping(ddr, dimm_params); in compute_fsl_memctl_config_regs()
2567 set_ddr_zq_cntl(ddr, zq_en); in compute_fsl_memctl_config_regs()
2568 set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts); in compute_fsl_memctl_config_regs()
2570 set_ddr_sr_cntr(ddr, sr_it); in compute_fsl_memctl_config_regs()
2574 ddr->debug[2] = 0x00000400; in compute_fsl_memctl_config_regs()
2575 ddr->debug[4] = 0xff800800; in compute_fsl_memctl_config_regs()
2576 ddr->debug[5] = 0x08000800; in compute_fsl_memctl_config_regs()
2577 ddr->debug[6] = 0x08000800; in compute_fsl_memctl_config_regs()
2578 ddr->debug[7] = 0x08000800; in compute_fsl_memctl_config_regs()
2579 ddr->debug[8] = 0x08000800; in compute_fsl_memctl_config_regs()
2583 ddr->debug[2] |= 0x00000200; /* set bit 22 */ in compute_fsl_memctl_config_regs()
2588 ddr->debug[28] = (ddr->debug[28] & 0xffffff00) | in compute_fsl_memctl_config_regs()
2592 return check_fsl_memctl_config_regs(ddr); in compute_fsl_memctl_config_regs()
2604 struct ccsr_ddr __iomem *ddr = in erratum_a009942_check_cpo() local
2607 u32 cpo_min = ddr_in32(&ddr->debug[9]) >> 24; in erratum_a009942_check_cpo()
2612 sdram_cfg = ddr_in32(&ddr->sdram_cfg); in erratum_a009942_check_cpo()
2625 cpo = ddr_in32(&ddr->debug[i]); in erratum_a009942_check_cpo()
2637 cpo = ddr_in32(&ddr->debug[13]); in erratum_a009942_check_cpo()
2645 cpo_target = ddr_in32(&ddr->debug[28]) & 0xff; in erratum_a009942_check_cpo()