Lines Matching refs:CONFIG_DIMM_SLOTS_PER_CTLR
50 #if (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
51 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
54 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
55 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
59 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
60 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
64 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
65 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
71 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
72 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
77 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
78 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
332 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { in __step_assign_addresses()
349 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { in __step_assign_addresses()
437 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { in __step_assign_addresses()
461 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { in __step_assign_addresses()
527 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { in fsl_ddr_compute()
574 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { in fsl_ddr_compute()
594 CONFIG_DIMM_SLOTS_PER_CTLR); in fsl_ddr_compute()
883 info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR; in fsl_ddr_sdram()
931 info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR; in fsl_ddr_sdram_size()