Lines Matching refs:cs

85 		cs_sa = (regs->cs[i].bnds >> 16) & 0xfff;  in fsl_ddr_set_memctl_regs()
86 		cs_ea = regs->cs[i].bnds & 0xfff;  in fsl_ddr_set_memctl_regs()
89 			csn_bnds_backup = regs->cs[i].bnds;  in fsl_ddr_set_memctl_regs()
90 			csn_bnds_t = (unsigned int *) &regs->cs[i].bnds;  in fsl_ddr_set_memctl_regs()
92 				*csn_bnds_t = regs->cs[i].bnds + 0x01000000;  in fsl_ddr_set_memctl_regs()
94 				*csn_bnds_t = regs->cs[i].bnds + 0x01000100;  in fsl_ddr_set_memctl_regs()
97 				csn, csn_bnds_backup, regs->cs[i].bnds);  in fsl_ddr_set_memctl_regs()
104 			out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);  in fsl_ddr_set_memctl_regs()
105 			out_be32(&ddr->cs0_config, regs->cs[i].config);  in fsl_ddr_set_memctl_regs()
106 			out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);  in fsl_ddr_set_memctl_regs()
109 			out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);  in fsl_ddr_set_memctl_regs()
110 			out_be32(&ddr->cs1_config, regs->cs[i].config);  in fsl_ddr_set_memctl_regs()
111 			out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);  in fsl_ddr_set_memctl_regs()
114 			out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);  in fsl_ddr_set_memctl_regs()
115 			out_be32(&ddr->cs2_config, regs->cs[i].config);  in fsl_ddr_set_memctl_regs()
116 			out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);  in fsl_ddr_set_memctl_regs()
119 			out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);  in fsl_ddr_set_memctl_regs()
120 			out_be32(&ddr->cs3_config, regs->cs[i].config);  in fsl_ddr_set_memctl_regs()
121 			out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);  in fsl_ddr_set_memctl_regs()
240 			if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))  in fsl_ddr_set_memctl_regs()
260 			if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))  in fsl_ddr_set_memctl_regs()
280 			if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))  in fsl_ddr_set_memctl_regs()
300 			if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))  in fsl_ddr_set_memctl_regs()
320 			if (!(regs->cs[2].config & SDRAM_CS_CONFIG_EN))  in fsl_ddr_set_memctl_regs()
454 		if (!(regs->cs[i].config & 0x80000000))  in fsl_ddr_set_memctl_regs()
457 			((regs->cs[i].config >> 14) & 0x3) + 2 +  in fsl_ddr_set_memctl_regs()
458 			((regs->cs[i].config >> 8) & 0x7) + 12 +  in fsl_ddr_set_memctl_regs()
459 			((regs->cs[i].config >> 0) & 0x7) + 8 +  in fsl_ddr_set_memctl_regs()
465 	else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */  in fsl_ddr_set_memctl_regs()
577 		csn_bnds_t = (unsigned int *) &regs->cs[csn].bnds;  in fsl_ddr_set_memctl_regs()
580 			csn, regs->cs[csn].bnds);  in fsl_ddr_set_memctl_regs()
584 			out_be32(&ddr->cs0_bnds, regs->cs[csn].bnds);  in fsl_ddr_set_memctl_regs()
587 			out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds);  in fsl_ddr_set_memctl_regs()
591 			out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds);  in fsl_ddr_set_memctl_regs()
594 			out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds);  in fsl_ddr_set_memctl_regs()