Lines Matching refs:ddr
30 struct ccsr_ddr __iomem *ddr; in fsl_ddr_set_memctl_regs() local
55 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; in fsl_ddr_set_memctl_regs()
59 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; in fsl_ddr_set_memctl_regs()
64 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; in fsl_ddr_set_memctl_regs()
69 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; in fsl_ddr_set_memctl_regs()
81 out_be32(&ddr->eor, regs->ddr_eor); in fsl_ddr_set_memctl_regs()
104 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
105 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
106 out_be32(&ddr->cs0_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
109 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
110 out_be32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
111 out_be32(&ddr->cs1_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
114 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
115 out_be32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
116 out_be32(&ddr->cs2_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
119 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
120 out_be32(&ddr->cs3_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
121 out_be32(&ddr->cs3_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
125 out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3); in fsl_ddr_set_memctl_regs()
126 out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); in fsl_ddr_set_memctl_regs()
127 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); in fsl_ddr_set_memctl_regs()
128 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); in fsl_ddr_set_memctl_regs()
129 out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); in fsl_ddr_set_memctl_regs()
130 out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); in fsl_ddr_set_memctl_regs()
131 out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); in fsl_ddr_set_memctl_regs()
132 out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); in fsl_ddr_set_memctl_regs()
133 out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); in fsl_ddr_set_memctl_regs()
134 out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); in fsl_ddr_set_memctl_regs()
135 out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); in fsl_ddr_set_memctl_regs()
136 out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); in fsl_ddr_set_memctl_regs()
137 out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); in fsl_ddr_set_memctl_regs()
138 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); in fsl_ddr_set_memctl_regs()
139 out_be32(&ddr->sdram_data_init, regs->ddr_data_init); in fsl_ddr_set_memctl_regs()
140 out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); in fsl_ddr_set_memctl_regs()
141 out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4); in fsl_ddr_set_memctl_regs()
142 out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5); in fsl_ddr_set_memctl_regs()
143 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); in fsl_ddr_set_memctl_regs()
144 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); in fsl_ddr_set_memctl_regs()
152 out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); in fsl_ddr_set_memctl_regs()
154 out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); in fsl_ddr_set_memctl_regs()
157 out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); in fsl_ddr_set_memctl_regs()
158 out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); in fsl_ddr_set_memctl_regs()
159 out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); in fsl_ddr_set_memctl_regs()
160 out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1); in fsl_ddr_set_memctl_regs()
163 out_be32(&ddr->sdram_cfg_2, in fsl_ddr_set_memctl_regs()
165 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); in fsl_ddr_set_memctl_regs()
166 out_be32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA); in fsl_ddr_set_memctl_regs()
169 out_be32(&ddr->ddr_cdr2, in fsl_ddr_set_memctl_regs()
174 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); in fsl_ddr_set_memctl_regs()
175 out_be32(&ddr->init_addr, regs->ddr_init_addr); in fsl_ddr_set_memctl_regs()
176 out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); in fsl_ddr_set_memctl_regs()
177 out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2); in fsl_ddr_set_memctl_regs()
179 out_be32(&ddr->err_disable, regs->err_disable); in fsl_ddr_set_memctl_regs()
180 out_be32(&ddr->err_int_en, regs->err_int_en); in fsl_ddr_set_memctl_regs()
184 out_be32(&ddr->debug[i], regs->debug[i]); in fsl_ddr_set_memctl_regs()
189 out_be32(&ddr->debug[12], 0x00000015); in fsl_ddr_set_memctl_regs()
190 out_be32(&ddr->debug[21], 0x24000000); in fsl_ddr_set_memctl_regs()
210 out_be32(&ddr->sdram_cfg, temp_sdram_cfg); in fsl_ddr_set_memctl_regs()
214 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff); in fsl_ddr_set_memctl_regs()
215 out_be32(&ddr->debug[2], 0x00000400); in fsl_ddr_set_memctl_regs()
216 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff); in fsl_ddr_set_memctl_regs()
217 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff); in fsl_ddr_set_memctl_regs()
218 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb); in fsl_ddr_set_memctl_regs()
219 out_be32(&ddr->mtcr, 0); in fsl_ddr_set_memctl_regs()
220 save1 = in_be32(&ddr->debug[12]); in fsl_ddr_set_memctl_regs()
221 save2 = in_be32(&ddr->debug[21]); in fsl_ddr_set_memctl_regs()
222 out_be32(&ddr->debug[12], 0x00000015); in fsl_ddr_set_memctl_regs()
223 out_be32(&ddr->debug[21], 0x24000000); in fsl_ddr_set_memctl_regs()
224 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff); in fsl_ddr_set_memctl_regs()
225 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN); in fsl_ddr_set_memctl_regs()
228 while (!(in_be32(&ddr->debug[1]) & 0x2)) in fsl_ddr_set_memctl_regs()
233 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
242 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) in fsl_ddr_set_memctl_regs()
244 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
253 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
262 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) in fsl_ddr_set_memctl_regs()
264 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
273 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
282 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) in fsl_ddr_set_memctl_regs()
284 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
293 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
302 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) in fsl_ddr_set_memctl_regs()
304 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
313 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
322 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) in fsl_ddr_set_memctl_regs()
324 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
335 while (in_be32(&ddr->sdram_md_cntl) & 0x80000000) in fsl_ddr_set_memctl_regs()
338 out_be32(&ddr->sdram_cfg, temp_sdram_cfg); in fsl_ddr_set_memctl_regs()
339 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); in fsl_ddr_set_memctl_regs()
340 out_be32(&ddr->debug[2], 0x0); in fsl_ddr_set_memctl_regs()
341 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); in fsl_ddr_set_memctl_regs()
342 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); in fsl_ddr_set_memctl_regs()
343 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); in fsl_ddr_set_memctl_regs()
344 out_be32(&ddr->debug[12], save1); in fsl_ddr_set_memctl_regs()
345 out_be32(&ddr->debug[21], save2); in fsl_ddr_set_memctl_regs()
346 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); in fsl_ddr_set_memctl_regs()
358 val32 = ddr_in32(&ddr->debug[28]); in fsl_ddr_set_memctl_regs()
360 ddr_out32(&ddr->debug[28], val32); in fsl_ddr_set_memctl_regs()
367 val32 = in_be32(&ddr->sdram_cfg_2) | 0x800; /* DDR_SLOW */ in fsl_ddr_set_memctl_regs()
368 out_be32(&ddr->sdram_cfg_2, val32); in fsl_ddr_set_memctl_regs()
370 val32 = in_be32(&ddr->debug[18]) | 0x2; in fsl_ddr_set_memctl_regs()
371 out_be32(&ddr->debug[18], val32); in fsl_ddr_set_memctl_regs()
373 out_be32(&ddr->debug[28], 0x30000000); in fsl_ddr_set_memctl_regs()
379 val32 = in_be32(&ddr->debug[28]); in fsl_ddr_set_memctl_regs()
390 out_be32(&ddr->debug[28], val32); in fsl_ddr_set_memctl_regs()
400 if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2) in fsl_ddr_set_memctl_regs()
401 && in_be32(&ddr->sdram_cfg) & 0x80000) { in fsl_ddr_set_memctl_regs()
403 setbits_be32(&ddr->debug[0], 1); in fsl_ddr_set_memctl_regs()
418 setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT); in fsl_ddr_set_memctl_regs()
420 in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
423 setbits_be32(&ddr->debug[2], 0x400); in fsl_ddr_set_memctl_regs()
424 debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2])); in fsl_ddr_set_memctl_regs()
440 setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); in fsl_ddr_set_memctl_regs()
443 temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) | SDRAM_CFG_BI); in fsl_ddr_set_memctl_regs()
446 temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI); in fsl_ddr_set_memctl_regs()
449 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); in fsl_ddr_set_memctl_regs()
474 bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) in fsl_ddr_set_memctl_regs()
486 while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && in fsl_ddr_set_memctl_regs()
499 clrbits_be32(&ddr->debug[2], 0x400); in fsl_ddr_set_memctl_regs()
500 debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2])); in fsl_ddr_set_memctl_regs()
504 clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK); in fsl_ddr_set_memctl_regs()
506 in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
509 setbits_be32(&ddr->debug[0], 0x10000); in fsl_ddr_set_memctl_regs()
510 debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0])); in fsl_ddr_set_memctl_regs()
513 setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK); in fsl_ddr_set_memctl_regs()
515 in_be32(&ddr->timing_cfg_2)); in fsl_ddr_set_memctl_regs()
518 out_be32(&ddr->debug[5], 0x9f9f9f9f); in fsl_ddr_set_memctl_regs()
519 debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5])); in fsl_ddr_set_memctl_regs()
522 out_be32(&ddr->debug[6], 0x9f9f9f9f); in fsl_ddr_set_memctl_regs()
523 debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6])); in fsl_ddr_set_memctl_regs()
526 setbits_be32(&ddr->debug[1], 0x800); in fsl_ddr_set_memctl_regs()
527 debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1])); in fsl_ddr_set_memctl_regs()
530 while (in_be32(&ddr->debug[1]) & 0x800) in fsl_ddr_set_memctl_regs()
534 clrbits_be32(&ddr->debug[0], 0x10000); in fsl_ddr_set_memctl_regs()
535 debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0])); in fsl_ddr_set_memctl_regs()
538 setbits_be32(&ddr->sdram_cfg_2, in fsl_ddr_set_memctl_regs()
540 debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
544 setbits_be32(&ddr->debug[1], 0x400); in fsl_ddr_set_memctl_regs()
545 debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1])); in fsl_ddr_set_memctl_regs()
548 while (in_be32(&ddr->debug[1]) & 0x400) in fsl_ddr_set_memctl_regs()
556 setbits_be32(&ddr->sdram_cfg_2, in fsl_ddr_set_memctl_regs()
558 debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
563 while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && in fsl_ddr_set_memctl_regs()
581 setbits_be32(&ddr->sdram_cfg, 0x2); /* MEM_HALT */ in fsl_ddr_set_memctl_regs()
584 out_be32(&ddr->cs0_bnds, regs->cs[csn].bnds); in fsl_ddr_set_memctl_regs()
587 out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds); in fsl_ddr_set_memctl_regs()
591 out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds); in fsl_ddr_set_memctl_regs()
594 out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds); in fsl_ddr_set_memctl_regs()
598 clrbits_be32(&ddr->sdram_cfg, 0x2); in fsl_ddr_set_memctl_regs()
604 clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); in fsl_ddr_set_memctl_regs()