Lines Matching refs:debug
83 debug("Workaround for ERRATUM_DDR111_DDR134\n"); in fsl_ddr_set_memctl_regs()
95 debug("Found cs%d_bns (0x%08x) covering 0xff000000, " in fsl_ddr_set_memctl_regs()
182 if (regs->debug[i]) { in fsl_ddr_set_memctl_regs()
183 debug("Write to debug_%d as %08x\n", i+1, regs->debug[i]); in fsl_ddr_set_memctl_regs()
184 out_be32(&ddr->debug[i], regs->debug[i]); in fsl_ddr_set_memctl_regs()
189 out_be32(&ddr->debug[12], 0x00000015); in fsl_ddr_set_memctl_regs()
190 out_be32(&ddr->debug[21], 0x24000000); in fsl_ddr_set_memctl_regs()
212 debug("Workaround for ERRATUM_DDR_A003\n"); in fsl_ddr_set_memctl_regs()
215 out_be32(&ddr->debug[2], 0x00000400); in fsl_ddr_set_memctl_regs()
220 save1 = in_be32(&ddr->debug[12]); in fsl_ddr_set_memctl_regs()
221 save2 = in_be32(&ddr->debug[21]); in fsl_ddr_set_memctl_regs()
222 out_be32(&ddr->debug[12], 0x00000015); in fsl_ddr_set_memctl_regs()
223 out_be32(&ddr->debug[21], 0x24000000); in fsl_ddr_set_memctl_regs()
228 while (!(in_be32(&ddr->debug[1]) & 0x2)) in fsl_ddr_set_memctl_regs()
340 out_be32(&ddr->debug[2], 0x0); in fsl_ddr_set_memctl_regs()
344 out_be32(&ddr->debug[12], save1); in fsl_ddr_set_memctl_regs()
345 out_be32(&ddr->debug[21], save2); in fsl_ddr_set_memctl_regs()
358 val32 = ddr_in32(&ddr->debug[28]); in fsl_ddr_set_memctl_regs()
360 ddr_out32(&ddr->debug[28], val32); in fsl_ddr_set_memctl_regs()
362 debug("Applied errata CONFIG_SYS_FSL_ERRATUM_A008378\n"); in fsl_ddr_set_memctl_regs()
370 val32 = in_be32(&ddr->debug[18]) | 0x2; in fsl_ddr_set_memctl_regs()
371 out_be32(&ddr->debug[18], val32); in fsl_ddr_set_memctl_regs()
373 out_be32(&ddr->debug[28], 0x30000000); in fsl_ddr_set_memctl_regs()
374 debug("Applied errta CONFIG_SYS_FSL_ERRATUM_A008109\n"); in fsl_ddr_set_memctl_regs()
379 val32 = in_be32(&ddr->debug[28]); in fsl_ddr_set_memctl_regs()
390 out_be32(&ddr->debug[28], val32); in fsl_ddr_set_memctl_regs()
391 debug("Applied errata CONFIG_SYS_FSL_ERRATUM_A009942\n"); in fsl_ddr_set_memctl_regs()
399 debug("Workaround for ERRATUM_DDR_115\n"); in fsl_ddr_set_memctl_regs()
403 setbits_be32(&ddr->debug[0], 1); in fsl_ddr_set_memctl_regs()
407 debug("Workaround for ERRATUM_DDR111_DDR134\n"); in fsl_ddr_set_memctl_regs()
415 debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr)); in fsl_ddr_set_memctl_regs()
419 debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n", in fsl_ddr_set_memctl_regs()
423 setbits_be32(&ddr->debug[2], 0x400); in fsl_ddr_set_memctl_regs()
424 debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2])); in fsl_ddr_set_memctl_regs()
482 debug("total %d GB\n", total_gb_size_per_controller); in fsl_ddr_set_memctl_regs()
483 debug("Need to wait up to %d * 10ms\n", timeout); in fsl_ddr_set_memctl_regs()
499 clrbits_be32(&ddr->debug[2], 0x400); in fsl_ddr_set_memctl_regs()
500 debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2])); in fsl_ddr_set_memctl_regs()
505 debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n", in fsl_ddr_set_memctl_regs()
509 setbits_be32(&ddr->debug[0], 0x10000); in fsl_ddr_set_memctl_regs()
510 debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0])); in fsl_ddr_set_memctl_regs()
514 debug("Setting TMING_CFG_2[CPO] to 0x%08x\n", in fsl_ddr_set_memctl_regs()
518 out_be32(&ddr->debug[5], 0x9f9f9f9f); in fsl_ddr_set_memctl_regs()
519 debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5])); in fsl_ddr_set_memctl_regs()
522 out_be32(&ddr->debug[6], 0x9f9f9f9f); in fsl_ddr_set_memctl_regs()
523 debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6])); in fsl_ddr_set_memctl_regs()
526 setbits_be32(&ddr->debug[1], 0x800); in fsl_ddr_set_memctl_regs()
527 debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1])); in fsl_ddr_set_memctl_regs()
530 while (in_be32(&ddr->debug[1]) & 0x800) in fsl_ddr_set_memctl_regs()
534 clrbits_be32(&ddr->debug[0], 0x10000); in fsl_ddr_set_memctl_regs()
535 debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0])); in fsl_ddr_set_memctl_regs()
540 debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
544 setbits_be32(&ddr->debug[1], 0x400); in fsl_ddr_set_memctl_regs()
545 debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1])); in fsl_ddr_set_memctl_regs()
548 while (in_be32(&ddr->debug[1]) & 0x400) in fsl_ddr_set_memctl_regs()
552 debug("Wait for %d * 10ms\n", timeout_save); in fsl_ddr_set_memctl_regs()
558 debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
562 debug("Need to wait up to %d * 10ms\n", timeout); in fsl_ddr_set_memctl_regs()
574 debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr)); in fsl_ddr_set_memctl_regs()
579 debug("Change cs%d_bnds back to 0x%08x\n", in fsl_ddr_set_memctl_regs()