Lines Matching refs:MAX_INTERFACE_NUM
39 enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
350 u32 data_read[MAX_INTERFACE_NUM]; in hws_ddr3_tip_init_controller()
366 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in hws_ddr3_tip_init_controller()
650 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in hws_ddr3_tip_init_controller()
1021 u32 read_data[MAX_INTERFACE_NUM]; in ddr3_tip_if_polling()
1028 end_if = MAX_INTERFACE_NUM - 1; in ddr3_tip_if_polling()
1102 end_if = MAX_INTERFACE_NUM - 1; in ddr3_tip_bus_read_modify_write()
1214 u32 cs_mask[MAX_INTERFACE_NUM]; in ddr3_tip_freq_set()
1229 end_if = MAX_INTERFACE_NUM - 1; in ddr3_tip_freq_set()
1237 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_freq_set()
1775 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_write_cs_result()
1816 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_write_mrs_cmd()
1824 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_write_mrs_cmd()
1885 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_ddr3_reset_phy_regs()
1987 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_adll_regs_bypass()
2037 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) { in ddr3_tip_ddr3_training_main_flow()
2480 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_ddr3_auto_tune()
2505 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_ddr3_auto_tune()
2552 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_enable_init_sequence()