Lines Matching refs:dev_num
92 static int ddr3_tip_ddr3_training_main_flow(u32 dev_num);
93 static int ddr3_tip_write_odt(u32 dev_num, enum hws_access_type access_type,
95 static int ddr3_tip_ddr3_auto_tune(u32 dev_num);
98 static int odt_test(u32 dev_num, enum hws_algo_type algo_type);
101 int adll_calibration(u32 dev_num, enum hws_access_type access_type,
103 static int ddr3_tip_set_timing(u32 dev_num, enum hws_access_type access_type,
225 static int ddr3_tip_rank_control(u32 dev_num, u32 if_id);
230 int ddr3_tip_tune_training_params(u32 dev_num, in ddr3_tip_tune_training_params() argument
276 int ddr3_tip_configure_cs(u32 dev_num, u32 if_id, u32 cs_num, u32 enable) in ddr3_tip_configure_cs() argument
292 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_configure_cs()
299 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_configure_cs()
306 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_configure_cs()
312 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_configure_cs()
321 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_configure_cs()
327 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_configure_cs()
338 int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_prm) in hws_ddr3_tip_init_controller() argument
351 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); in hws_ddr3_tip_init_controller()
362 CHECK_STATUS(ddr3_tip_configure_phy(dev_num)); in hws_ddr3_tip_init_controller()
382 (dev_num, ACCESS_TYPE_MULTICAST, in hws_ddr3_tip_init_controller()
402 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
408 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
413 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
418 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
429 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
434 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
442 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
446 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
452 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
454 if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_TIP_REV) < MV_TIP_REV_3) { in hws_ddr3_tip_init_controller()
458 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
498 ddr3_tip_configure_cs(dev_num, if_id, cs_cnt, in hws_ddr3_tip_init_controller()
531 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
535 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
544 (dev_num, ACCESS_TYPE_MULTICAST, in hws_ddr3_tip_init_controller()
561 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
567 ddr3_tip_write_odt(dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
569 ddr3_tip_set_timing(dev_num, access_type, if_id, freq); in hws_ddr3_tip_init_controller()
571 if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_TIP_REV) < MV_TIP_REV_3) { in hws_ddr3_tip_init_controller()
573 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
578 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
589 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
606 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
610 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
613 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
619 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
623 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
628 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
634 (dev_num, ACCESS_TYPE_MULTICAST, in hws_ddr3_tip_init_controller()
638 if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_TIP_REV) == MV_TIP_REV_3) { in hws_ddr3_tip_init_controller()
640 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
644 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
652 CHECK_STATUS(ddr3_tip_rank_control(dev_num, if_id)); in hws_ddr3_tip_init_controller()
659 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
662 (dev_num, access_type, if_id, in hws_ddr3_tip_init_controller()
670 ddr3_tip_cmd_addr_init_delay(dev_num, adll_tap); in hws_ddr3_tip_init_controller()
679 static int ddr3_tip_rev2_rank_control(u32 dev_num, u32 if_id) in ddr3_tip_rev2_rank_control() argument
682 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); in ddr3_tip_rev2_rank_control()
727 (dev_num, ACCESS_TYPE_UNICAST, if_id, DDR3_RANK_CTRL_REG, in ddr3_tip_rev2_rank_control()
733 static int ddr3_tip_rev3_rank_control(u32 dev_num, u32 if_id) in ddr3_tip_rev3_rank_control() argument
736 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); in ddr3_tip_rev3_rank_control()
760 (dev_num, ACCESS_TYPE_UNICAST, if_id, DDR3_RANK_CTRL_REG, in ddr3_tip_rev3_rank_control()
766 static int ddr3_tip_rank_control(u32 dev_num, u32 if_id) in ddr3_tip_rank_control() argument
768 if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_TIP_REV) == MV_TIP_REV_2) in ddr3_tip_rank_control()
769 return ddr3_tip_rev2_rank_control(dev_num, if_id); in ddr3_tip_rank_control()
771 return ddr3_tip_rev3_rank_control(dev_num, if_id); in ddr3_tip_rank_control()
801 int ddr3_tip_validate_algo_components(u8 dev_num) in ddr3_tip_validate_algo_components() argument
821 status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].tip_dunit_mux_select_func, in ddr3_tip_validate_algo_components()
823 status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].mv_ddr_dunit_write, in ddr3_tip_validate_algo_components()
825 status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].mv_ddr_dunit_read, in ddr3_tip_validate_algo_components()
827 status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].mv_ddr_phy_write, in ddr3_tip_validate_algo_components()
829 status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].mv_ddr_phy_read, in ddr3_tip_validate_algo_components()
831 status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].tip_get_freq_config_info_func, in ddr3_tip_validate_algo_components()
833 status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].tip_set_freq_divider_func, in ddr3_tip_validate_algo_components()
835 status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].tip_get_clock_ratio, in ddr3_tip_validate_algo_components()
906 int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type) in hws_ddr3_tip_run_alg() argument
918 return odt_test(dev_num, algo_type); in hws_ddr3_tip_run_alg()
922 status = ddr3_tip_ddr3_auto_tune(dev_num); in hws_ddr3_tip_run_alg()
945 static int odt_test(u32 dev_num, enum hws_algo_type algo_type) in odt_test() argument
967 ret = ddr3_tip_ddr3_auto_tune(dev_num); in odt_test()
985 int hws_ddr3_tip_select_ddr_controller(u32 dev_num, int enable) in hws_ddr3_tip_select_ddr_controller() argument
987 return config_func_info[dev_num]. in hws_ddr3_tip_select_ddr_controller()
988 tip_dunit_mux_select_func((u8)dev_num, enable); in hws_ddr3_tip_select_ddr_controller()
994 int ddr3_tip_if_write(u32 dev_num, enum hws_access_type interface_access, in ddr3_tip_if_write() argument
997 config_func_info[dev_num].mv_ddr_dunit_write(reg_addr, mask, data_value); in ddr3_tip_if_write()
1005 int ddr3_tip_if_read(u32 dev_num, enum hws_access_type interface_access, in ddr3_tip_if_read() argument
1008 config_func_info[dev_num].mv_ddr_dunit_read(reg_addr, mask, data); in ddr3_tip_if_read()
1016 int ddr3_tip_if_polling(u32 dev_num, enum hws_access_type access_type, in ddr3_tip_if_polling() argument
1041 ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, in ddr3_tip_if_polling()
1068 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, in ddr3_tip_bus_read() argument
1072 return config_func_info[dev_num]. in ddr3_tip_bus_read()
1079 int ddr3_tip_bus_write(u32 dev_num, enum hws_access_type interface_access, in ddr3_tip_bus_write() argument
1084 return config_func_info[dev_num]. in ddr3_tip_bus_write()
1092 int ddr3_tip_bus_read_modify_write(u32 dev_num, enum hws_access_type access_type, in ddr3_tip_bus_read_modify_write() argument
1111 (dev_num, if_id, ACCESS_TYPE_UNICAST, phy_id, in ddr3_tip_bus_read_modify_write()
1115 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_bus_read_modify_write()
1126 int adll_calibration(u32 dev_num, enum hws_access_type access_type, in adll_calibration() argument
1131 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); in adll_calibration()
1136 (dev_num, access_type, if_id, SDRAM_CFG_REG, in adll_calibration()
1140 (dev_num, access_type, if_id, SDRAM_CFG_REG, in adll_calibration()
1143 CHECK_STATUS(config_func_info[dev_num]. in adll_calibration()
1144 tip_get_freq_config_info_func((u8)dev_num, frequency, in adll_calibration()
1150 (dev_num, access_type, if_id, bus_cnt, in adll_calibration()
1154 (dev_num, access_type, if_id, bus_cnt, in adll_calibration()
1161 (dev_num, ACCESS_TYPE_UNICAST, if_id, bus_cnt, in adll_calibration()
1165 (dev_num, ACCESS_TYPE_UNICAST, if_id, bus_cnt, in adll_calibration()
1172 (dev_num, access_type, if_id, DRAM_PHY_CFG_REG, in adll_calibration()
1176 (dev_num, access_type, if_id, DRAM_PHY_CFG_REG, in adll_calibration()
1180 if (ddr3_tip_if_polling(dev_num, access_type, if_id, in adll_calibration()
1189 (dev_num, access_type, if_id, SDRAM_CFG_REG, in adll_calibration()
1193 (dev_num, access_type, if_id, SDRAM_CFG_REG, in adll_calibration()
1199 int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type, in ddr3_tip_freq_set() argument
1215 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); in ddr3_tip_freq_set()
1222 ("dev %d access %d IF %d freq %d\n", dev_num, in ddr3_tip_freq_set()
1242 ddr3_tip_calc_cs_mask(dev_num, if_id, effective_cs, in ddr3_tip_freq_set()
1282 dev_num, access_type, if_id, in ddr3_tip_freq_set()
1302 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, in ddr3_tip_freq_set()
1310 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1314 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1319 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1323 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1329 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1332 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1335 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1338 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1344 (dev_num, access_type, if_id, DFS_REG, 0x4, in ddr3_tip_freq_set()
1347 if (ddr3_tip_if_polling(dev_num, ACCESS_TYPE_UNICAST, in ddr3_tip_freq_set()
1366 if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_INTERLEAVE_WA) == 1) { in ddr3_tip_freq_set()
1368 if (config_func_info[dev_num].tip_get_clock_ratio(frequency) == 1) { in ddr3_tip_freq_set()
1371 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1377 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1381 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_freq_set()
1385 config_func_info[dev_num].tip_set_freq_divider_func(dev_num, if_id, in ddr3_tip_freq_set()
1390 (dev_num, access_type, if_id, DFS_REG, in ddr3_tip_freq_set()
1393 (dev_num, access_type, if_id, DFS_REG, in ddr3_tip_freq_set()
1402 (dev_num, access_type, if_id, DFS_REG, in ddr3_tip_freq_set()
1408 (dev_num, access_type, if_id, 0x1874, in ddr3_tip_freq_set()
1411 (dev_num, access_type, if_id, 0x1884, in ddr3_tip_freq_set()
1414 (dev_num, access_type, if_id, 0x1894, in ddr3_tip_freq_set()
1417 (dev_num, access_type, if_id, 0x18a4, in ddr3_tip_freq_set()
1423 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1427 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1431 CHECK_STATUS(config_func_info[dev_num]. in ddr3_tip_freq_set()
1432 tip_get_freq_config_info_func(dev_num, frequency, in ddr3_tip_freq_set()
1440 (dev_num, ACCESS_TYPE_UNICAST, in ddr3_tip_freq_set()
1448 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_freq_set()
1455 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1460 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1466 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x3ff03ff, in ddr3_tip_freq_set()
1475 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1479 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1483 ddr3_tip_set_timing(dev_num, access_type, if_id, frequency); in ddr3_tip_freq_set()
1486 ddr3_tip_cmd_addr_init_delay(dev_num, adll_tap); in ddr3_tip_freq_set()
1491 (dev_num, access_type, if_id, DFS_REG, 0, in ddr3_tip_freq_set()
1494 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0, 0x8, DFS_REG, in ddr3_tip_freq_set()
1502 (dev_num, access_type, if_id, in ddr3_tip_freq_set()
1505 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0, 0x1f, in ddr3_tip_freq_set()
1513 (dev_num, access_type, if_id, DFS_REG, 0, in ddr3_tip_freq_set()
1517 (dev_num, access_type, if_id, DUNIT_MMASK_REG, in ddr3_tip_freq_set()
1525 (dev_num, access_type, if_id, MR0_REG, in ddr3_tip_freq_set()
1536 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, in ddr3_tip_freq_set()
1544 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, in ddr3_tip_freq_set()
1548 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, in ddr3_tip_freq_set()
1556 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, DUNIT_ODT_CTRL_REG, 0xf, 0xf)); in ddr3_tip_freq_set()
1559 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, DUNIT_ODT_CTRL_REG, in ddr3_tip_freq_set()
1569 CHECK_STATUS(ddr3_tip_write_mrs_cmd(dev_num, cs_mask, MR_CMD0, in ddr3_tip_freq_set()
1574 CHECK_STATUS(ddr3_tip_write_mrs_cmd(dev_num, cs_mask, MR_CMD2, in ddr3_tip_freq_set()
1578 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, in ddr3_tip_freq_set()
1591 static int ddr3_tip_write_odt(u32 dev_num, enum hws_access_type access_type, in ddr3_tip_write_odt() argument
1602 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_write_odt()
1605 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_write_odt()
1608 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, in ddr3_tip_write_odt()
1615 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_write_odt()
1624 static int ddr3_tip_set_timing(u32 dev_num, enum hws_access_type access_type, in ddr3_tip_set_timing() argument
1643 t_hclk = MEGA / (freq / config_func_info[dev_num].tip_get_clock_ratio(frequency)); in ddr3_tip_set_timing()
1717 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_set_timing()
1744 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_set_timing()
1747 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_set_timing()
1751 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_set_timing()
1755 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, DDR_TIMING_REG, in ddr3_tip_set_timing()
1769 int ddr3_tip_write_cs_result(u32 dev_num, u32 offset) in ddr3_tip_write_cs_result() argument
1772 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); in ddr3_tip_write_cs_result()
1785 ddr3_tip_bus_read(dev_num, if_id, in ddr3_tip_write_cs_result()
1791 ddr3_tip_bus_write(dev_num, in ddr3_tip_write_cs_result()
1809 int ddr3_tip_write_mrs_cmd(u32 dev_num, u32 *cs_mask_arr, enum mr_number mr_num, u32 data, u32 mask) in ddr3_tip_write_mrs_cmd() argument
1814 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_write_mrs_cmd()
1819 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_write_mrs_cmd()
1826 if (ddr3_tip_if_polling(dev_num, ACCESS_TYPE_UNICAST, if_id, 0, in ddr3_tip_write_mrs_cmd()
1840 int ddr3_tip_reset_fifo_ptr(u32 dev_num) in ddr3_tip_reset_fifo_ptr() argument
1845 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_reset_fifo_ptr()
1851 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_reset_fifo_ptr()
1855 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_reset_fifo_ptr()
1859 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_reset_fifo_ptr()
1862 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_reset_fifo_ptr()
1866 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_reset_fifo_ptr()
1870 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_reset_fifo_ptr()
1879 int ddr3_tip_ddr3_reset_phy_regs(u32 dev_num) in ddr3_tip_ddr3_reset_phy_regs() argument
1882 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); in ddr3_tip_ddr3_reset_phy_regs()
1891 (dev_num, ACCESS_TYPE_UNICAST, in ddr3_tip_ddr3_reset_phy_regs()
1897 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_ddr3_reset_phy_regs()
1902 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_ddr3_reset_phy_regs()
1906 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_ddr3_reset_phy_regs()
1910 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_ddr3_reset_phy_regs()
1914 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_ddr3_reset_phy_regs()
1918 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_ddr3_reset_phy_regs()
1922 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_ddr3_reset_phy_regs()
1926 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_ddr3_reset_phy_regs()
1930 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_ddr3_reset_phy_regs()
1940 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, in ddr3_tip_ddr3_reset_phy_regs()
1951 int ddr3_tip_restore_dunit_regs(u32 dev_num) in ddr3_tip_restore_dunit_regs() argument
1957 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_restore_dunit_regs()
1960 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_restore_dunit_regs()
1964 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_restore_dunit_regs()
1972 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, in ddr3_tip_restore_dunit_regs()
1981 int ddr3_tip_adll_regs_bypass(u32 dev_num, u32 reg_val1, u32 reg_val2) in ddr3_tip_adll_regs_bypass() argument
1984 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); in ddr3_tip_adll_regs_bypass()
1992 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_adll_regs_bypass()
1996 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_adll_regs_bypass()
2008 static int ddr3_tip_ddr3_training_main_flow(u32 dev_num) in ddr3_tip_ddr3_training_main_flow() argument
2022 CHECK_STATUS(print_device_info((u8)dev_num)); in ddr3_tip_ddr3_training_main_flow()
2026 ddr3_tip_validate_algo_components(dev_num); in ddr3_tip_ddr3_training_main_flow()
2029 CHECK_STATUS(ddr3_tip_ddr3_reset_phy_regs(dev_num)); in ddr3_tip_ddr3_training_main_flow()
2039 config_func_info[dev_num].tip_set_freq_divider_func( in ddr3_tip_ddr3_training_main_flow()
2040 (u8)dev_num, if_id, freq); in ddr3_tip_ddr3_training_main_flow()
2048 adll_calibration(dev_num, ACCESS_TYPE_MULTICAST, 0, freq); in ddr3_tip_ddr3_training_main_flow()
2054 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2065 ret = hws_ddr3_tip_init_controller(dev_num, &init_cntr_prm); in ddr3_tip_ddr3_training_main_flow()
2067 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2076 ret = adll_calibration(dev_num, ACCESS_TYPE_MULTICAST, 0, freq); in ddr3_tip_ddr3_training_main_flow()
2088 ddr3_tip_adll_regs_bypass(dev_num, 0, 0x1f); in ddr3_tip_ddr3_training_main_flow()
2096 ret = ddr3_tip_freq_set(dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_ddr3_training_main_flow()
2099 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2112 ret = ddr3_tip_dynamic_write_leveling(dev_num, 1); in ddr3_tip_ddr3_training_main_flow()
2114 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2129 ret = ddr3_tip_load_all_pattern_to_mem(dev_num); in ddr3_tip_ddr3_training_main_flow()
2131 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2144 ddr3_tip_adll_regs_bypass(dev_num, phy_reg1_val, 0); in ddr3_tip_ddr3_training_main_flow()
2158 ddr3_tip_freq_set(dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_ddr3_training_main_flow()
2161 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2175 ret = ddr3_tip_dynamic_write_leveling(dev_num, 0); in ddr3_tip_ddr3_training_main_flow()
2178 ret = ddr3_tip_legacy_dynamic_write_leveling(dev_num); in ddr3_tip_ddr3_training_main_flow()
2182 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2197 ret = ddr3_tip_load_all_pattern_to_mem(dev_num); in ddr3_tip_ddr3_training_main_flow()
2199 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2217 ret = ddr3_tip_dynamic_read_leveling(dev_num, medium_freq); in ddr3_tip_ddr3_training_main_flow()
2220 ret = ddr3_tip_legacy_dynamic_read_leveling(dev_num); in ddr3_tip_ddr3_training_main_flow()
2224 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2237 ret = ddr3_tip_dynamic_write_leveling_supp(dev_num); in ddr3_tip_ddr3_training_main_flow()
2239 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2254 ret = ddr3_tip_pbs_rx(dev_num); in ddr3_tip_ddr3_training_main_flow()
2256 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2273 ret = ddr3_tip_pbs_tx(dev_num); in ddr3_tip_ddr3_training_main_flow()
2275 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2295 ret = ddr3_tip_freq_set(dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_ddr3_training_main_flow()
2300 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2313 ret = ddr3_tip_dynamic_write_leveling(dev_num, 0); in ddr3_tip_ddr3_training_main_flow()
2315 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2327 ret = ddr3_tip_load_all_pattern_to_mem(dev_num); in ddr3_tip_ddr3_training_main_flow()
2329 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2342 ret = ddr3_tip_dynamic_read_leveling(dev_num, tm-> in ddr3_tip_ddr3_training_main_flow()
2346 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2361 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2378 ret = ddr3_tip_vref(dev_num); in ddr3_tip_ddr3_training_main_flow()
2382 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2401 ret = ddr3_tip_centralization_rx(dev_num); in ddr3_tip_ddr3_training_main_flow()
2403 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2422 ret = ddr3_tip_dynamic_write_leveling_supp(dev_num); in ddr3_tip_ddr3_training_main_flow()
2424 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2444 ret = ddr3_tip_centralization_tx(dev_num); in ddr3_tip_ddr3_training_main_flow()
2446 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2461 CHECK_STATUS(ddr3_tip_restore_dunit_regs(dev_num)); in ddr3_tip_ddr3_training_main_flow()
2464 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_training_main_flow()
2472 static int ddr3_tip_ddr3_auto_tune(u32 dev_num) in ddr3_tip_ddr3_auto_tune() argument
2485 status = ddr3_tip_ddr3_training_main_flow(dev_num); in ddr3_tip_ddr3_auto_tune()
2489 run_xsb_test(dev_num, xsb_validation_base_address, 1, 1, in ddr3_tip_ddr3_auto_tune()
2494 ddr3_tip_reg_dump(dev_num); in ddr3_tip_ddr3_auto_tune()
2497 CHECK_STATUS(ddr3_tip_print_log(dev_num, window_mem_addr)); in ddr3_tip_ddr3_auto_tune()
2501 CHECK_STATUS(ddr3_tip_print_stability_log(dev_num)); in ddr3_tip_ddr3_auto_tune()
2541 int ddr3_tip_enable_init_sequence(u32 dev_num) in ddr3_tip_enable_init_sequence() argument
2545 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); in ddr3_tip_enable_init_sequence()
2549 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, 0, in ddr3_tip_enable_init_sequence()
2556 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0, 0x1, in ddr3_tip_enable_init_sequence()
2578 (dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_enable_init_sequence()
2587 int ddr3_tip_register_dq_table(u32 dev_num, u32 *table) in ddr3_tip_register_dq_table() argument