Lines Matching refs:tm
48 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); in mv_ddr_topology_map_update() local
49 struct if_params *iface_params = &(tm->interface_params[0]); in mv_ddr_topology_map_update()
60 if (tm->cfg_src == MV_DDR_CFG_SPD) { in mv_ddr_topology_map_update()
62 val = mv_ddr_spd_dev_type_get(&tm->spd_data); in mv_ddr_topology_map_update()
69 if (mv_ddr_spd_timing_calc(&tm->spd_data, tm->timing_data) > 0) { in mv_ddr_topology_map_update()
75 iface_params->bus_width = mv_ddr_spd_dev_width_get(&tm->spd_data); in mv_ddr_topology_map_update()
78 iface_params->memory_size = mv_ddr_spd_die_capacity_get(&tm->spd_data); in mv_ddr_topology_map_update()
81 tm->bus_act_mask = mv_ddr_bus_bit_mask_get(); in mv_ddr_topology_map_update()
84 val = mv_ddr_spd_cs_bit_mask_get(&tm->spd_data); in mv_ddr_topology_map_update()
89 val = mv_ddr_spd_module_type_get(&tm->spd_data); in mv_ddr_topology_map_update()
104 val = mv_ddr_spd_mem_mirror_get(&tm->spd_data); in mv_ddr_topology_map_update()
118 mv_ddr_spd_supported_cls_calc(&tm->spd_data); in mv_ddr_topology_map_update()
119 val = mv_ddr_cl_calc(tm->timing_data[MV_DDR_TAA_MIN], tclk); in mv_ddr_topology_map_update()
125 } else if (tm->cfg_src == MV_DDR_CFG_DEFAULT) { in mv_ddr_topology_map_update()
130 if (tm->twin_die_combined == COMBINED) { in mv_ddr_topology_map_update()
148 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); in mv_ddr_bus_bit_mask_get() local
151 if (tm->cfg_src == MV_DDR_CFG_SPD) { in mv_ddr_bus_bit_mask_get()
152 if (tm->bus_act_mask == MV_DDR_32BIT_ECC_PUP8_BUS_MASK) in mv_ddr_bus_bit_mask_get()
153 tm->spd_data.byte_fields.byte_13.bit_fields.primary_bus_width = MV_DDR_PRI_BUS_WIDTH_32; in mv_ddr_bus_bit_mask_get()
155 enum mv_ddr_pri_bus_width pri_bus_width = mv_ddr_spd_pri_bus_width_get(&tm->spd_data); in mv_ddr_bus_bit_mask_get()
156 enum mv_ddr_bus_width_ext bus_width_ext = mv_ddr_spd_bus_width_ext_get(&tm->spd_data); in mv_ddr_bus_bit_mask_get()
181 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); in mv_ddr_if_bus_width_get() local
184 switch (tm->bus_act_mask) { in mv_ddr_if_bus_width_get()
211 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); in mv_ddr_cs_num_get() local
212 struct if_params *iface_params = &(tm->interface_params[0]); in mv_ddr_cs_num_get()
216 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, sphy); in mv_ddr_cs_num_get()
230 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); in mv_ddr_is_ecc_ena() local
232 if (DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask) || in mv_ddr_is_ecc_ena()
233 DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask) || in mv_ddr_is_ecc_ena()
234 DDR3_IS_ECC_PUP8_MODE(tm->bus_act_mask)) in mv_ddr_is_ecc_ena()
242 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); in mv_ddr_ck_delay_get() local
244 if (tm->ck_delay) in mv_ddr_ck_delay_get()
245 return tm->ck_delay; in mv_ddr_ck_delay_get()
266 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); in mv_ddr_mem_sz_per_cs_get() local
267 struct if_params *iface_params = &(tm->interface_params[0]); in mv_ddr_mem_sz_per_cs_get()
271 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, i); in mv_ddr_mem_sz_per_cs_get()
306 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); in mv_ddr_rtt_nom_get() local
307 unsigned int rtt_nom = tm->edata.mem_edata.rtt_nom; in mv_ddr_rtt_nom_get()
319 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); in mv_ddr_rtt_park_get() local
324 rtt_park = tm->edata.mem_edata.rtt_park[cs_num - 1]; in mv_ddr_rtt_park_get()
336 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); in mv_ddr_rtt_wr_get() local
341 rtt_wr = tm->edata.mem_edata.rtt_wr[cs_num - 1]; in mv_ddr_rtt_wr_get()
353 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); in mv_ddr_dic_get() local
354 unsigned int dic = tm->edata.mem_edata.dic; in mv_ddr_dic_get()