Lines Matching refs:cs
68 int ddr3_find_adll_limits(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc, int is_tx);
71 static int ddr3_center_calc(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc,
73 int ddr3_special_pattern_i_search(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc,
75 int ddr3_special_pattern_ii_search(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc,
77 int ddr3_set_dqs_centralization_results(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc,
133 u32 cs, ecc, reg; in ddr3_dqs_centralization_rx() local
151 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dqs_centralization_rx()
152 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dqs_centralization_rx()
154 (u32) cs, 1); in ddr3_dqs_centralization_rx()
172 status = ddr3_find_adll_limits(dram_info, cs, in ddr3_dqs_centralization_rx()
179 status = ddr3_center_calc(dram_info, cs, ecc, in ddr3_dqs_centralization_rx()
215 u32 cs, ecc, reg; in ddr3_dqs_centralization_tx() local
233 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dqs_centralization_tx()
234 if (dram_info->cs_ena & (1 << cs)) { in ddr3_dqs_centralization_tx()
236 (u32) cs, 1); in ddr3_dqs_centralization_tx()
252 status = ddr3_find_adll_limits(dram_info, cs, in ddr3_dqs_centralization_tx()
259 status = ddr3_center_calc(dram_info, cs, ecc, in ddr3_dqs_centralization_tx()
296 int ddr3_find_adll_limits(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc, int is_tx) in ddr3_find_adll_limits() argument
334 for (cs_tmp = 0; cs_tmp < cs; cs_tmp++) { in ddr3_find_adll_limits()
395 dram_info->wl_val[cs] in ddr3_find_adll_limits()
398 ddr3_write_pup_reg(adll_addr, cs, pup + in ddr3_find_adll_limits()
453 DEBUG_DQS_D(cs, 1); in ddr3_find_adll_limits()
568 DEBUG_DQS_D(cs, 1); in ddr3_find_adll_limits()
712 DEBUG_PER_DQ_C("DDR3 - TX CS: ", cs, 1); in ddr3_find_adll_limits()
714 DEBUG_PER_DQ_C("DDR3 - RX CS: ", cs, 1); in ddr3_find_adll_limits()
887 static int ddr3_center_calc(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc, in ddr3_center_calc() argument
926 ddr3_special_pattern_i_search(dram_info, cs, ecc, is_tx, in ddr3_center_calc()
935 ddr3_special_pattern_ii_search(dram_info, cs, ecc, is_tx, in ddr3_center_calc()
941 return ddr3_set_dqs_centralization_results(dram_info, cs, ecc, is_tx); in ddr3_center_calc()
952 int ddr3_special_pattern_i_search(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc, in ddr3_special_pattern_i_search() argument
980 sdram_offset = cs * SDRAM_CS_SIZE + SDRAM_DQS_RX_OFFS + in ddr3_special_pattern_i_search()
987 ddr3_write_pup_reg(PUP_DQS_RD, cs, in ddr3_special_pattern_i_search()
1089 cs, in ddr3_special_pattern_i_search()
1113 int ddr3_special_pattern_ii_search(MV_DRAM_INFO *dram_info, u32 cs, u32 ecc, in ddr3_special_pattern_ii_search() argument
1136 sdram_offset = cs * SDRAM_CS_SIZE + SDRAM_DQS_RX_OFFS; in ddr3_special_pattern_ii_search()
1147 ddr3_write_pup_reg(PUP_DQS_RD, cs, in ddr3_special_pattern_ii_search()
1240 cs, in ddr3_special_pattern_ii_search()
1262 int ddr3_set_dqs_centralization_results(MV_DRAM_INFO *dram_info, u32 cs, in ddr3_set_dqs_centralization_results() argument
1275 cs, 1); in ddr3_set_dqs_centralization_results()
1278 cs, 1); in ddr3_set_dqs_centralization_results()
1313 ddr3_write_pup_reg(PUP_DQS_WR, cs, pup_num, 0, in ddr3_set_dqs_centralization_results()
1315 dram_info->wl_val[cs][pup_num][D]); in ddr3_set_dqs_centralization_results()
1317 ddr3_write_pup_reg(PUP_DQS_RD, cs, pup_num, 0, in ddr3_set_dqs_centralization_results()
1330 u32 cs, cs_count, cs_tmp, victim_dq; in ddr3_load_dqs_patterns() local
1335 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_load_dqs_patterns()
1336 if (dram_info->cs_ena & (1 << cs)) { in ddr3_load_dqs_patterns()
1338 for (cs_tmp = 0; cs_tmp < cs; cs_tmp++) { in ddr3_load_dqs_patterns()