Lines Matching refs:dram_info
86 MV_DRAM_INFO dram_info; in ddr3_hw_training() local
94 memset(&dram_info, 0, sizeof(dram_info)); in ddr3_hw_training()
95 dram_info.num_cs = ddr3_get_cs_num_from_reg(); in ddr3_hw_training()
96 dram_info.cs_ena = ddr3_get_cs_ena_from_reg(); in ddr3_hw_training()
97 dram_info.target_frequency = target_freq; in ddr3_hw_training()
98 dram_info.ddr_width = ddr_width; in ddr3_hw_training()
99 dram_info.num_of_std_pups = ddr_width / PUP_SIZE; in ddr3_hw_training()
100 dram_info.rl400_bug = 0; in ddr3_hw_training()
101 dram_info.multi_cs_mr_support = 0; in ddr3_hw_training()
103 dram_info.rl400_bug = 1; in ddr3_hw_training()
109 dram_info.ecc_ena = 1; in ddr3_hw_training()
113 dram_info.ecc_ena = 0; in ddr3_hw_training()
118 dram_info.reg_dimm = 1; in ddr3_hw_training()
120 dram_info.reg_dimm = 0; in ddr3_hw_training()
122 dram_info.num_of_total_pups = ddr_width / PUP_SIZE + dram_info.ecc_ena; in ddr3_hw_training()
126 dram_info.mode_2t = (reg >> REG_DUNIT_CTRL_LOW_2T_OFFS) & in ddr3_hw_training()
137 dram_info.cl = ddr3_valid_cl_to_cl(reg); in ddr3_hw_training()
147 dram_info.cwl = reg; in ddr3_hw_training()
151 if ((dram_info.target_frequency > DDR_400) && (ddr3_run_pbs)) in ddr3_hw_training()
155 if ((dram_info.target_frequency > DDR_400) && (ddr3_run_pbs) && in ddr3_hw_training()
163 freq = dram_info.target_frequency; in ddr3_hw_training()
169 mv_sys_xor_init(&dram_info); in ddr3_hw_training()
191 if (dram_info.target_frequency > DFS_MARGIN) { in ddr3_hw_training()
195 if (dram_info.reg_dimm == 1) in ddr3_hw_training()
198 if (MV_OK != ddr3_dfs_high_2_low(freq, &dram_info)) { in ddr3_hw_training()
204 if ((dram_info.reg_dimm == 1) && in ddr3_hw_training()
208 &dram_info)) in ddr3_hw_training()
230 if (dram_info.cs_ena > 1) { in ddr3_hw_training()
234 &dram_info)) { in ddr3_hw_training()
241 &dram_info)) { in ddr3_hw_training()
248 freq, &dram_info)) { in ddr3_hw_training()
254 &dram_info)) { in ddr3_hw_training()
269 if (MV_OK != ddr3_load_patterns(&dram_info, 0)) { in ddr3_hw_training()
286 freq = dram_info.target_frequency; in ddr3_hw_training()
302 &dram_info)) { in ddr3_hw_training()
321 if (dram_info.cs_ena > 1) { in ddr3_hw_training()
323 freq, tmp_ratio, &dram_info)) { in ddr3_hw_training()
329 freq, &dram_info)) { in ddr3_hw_training()
335 if ((dram_info.reg_dimm == 1) && in ddr3_hw_training()
339 freq, &dram_info)) in ddr3_hw_training()
344 freq, &dram_info)) { in ddr3_hw_training()
348 freq, tmp_ratio, &dram_info)) { in ddr3_hw_training()
368 if (freq == DDR_400 && dram_info.rl400_bug) { in ddr3_hw_training()
370 &dram_info); in ddr3_hw_training()
378 freq, &dram_info)) { in ddr3_hw_training()
383 &dram_info)) { in ddr3_hw_training()
396 if (MV_OK != ddr3_wl_supplement(&dram_info)) { in ddr3_hw_training()
410 status = ddr3_pbs_rx(&dram_info); in ddr3_hw_training()
419 status = ddr3_pbs_tx(&dram_info); in ddr3_hw_training()
430 } while (freq != dram_info.target_frequency); in ddr3_hw_training()
432 status = ddr3_dqs_centralization_rx(&dram_info); in ddr3_hw_training()
441 status = ddr3_dqs_centralization_tx(&dram_info); in ddr3_hw_training()
451 ddr3_set_performance_params(&dram_info); in ddr3_hw_training()
453 if (dram_info.ecc_ena) { in ddr3_hw_training()
456 dram_info.num_cs = 1; in ddr3_hw_training()
457 dram_info.cs_ena = 1; in ddr3_hw_training()
458 mv_sys_xor_init(&dram_info); in ddr3_hw_training()
475 ddr3_save_training(&dram_info); in ddr3_hw_training()
481 ddr3_odt_read_dynamic_config(&dram_info); in ddr3_hw_training()
486 void ddr3_set_performance_params(MV_DRAM_INFO *dram_info) in ddr3_set_performance_params() argument
491 DEBUG_MAIN_FULL_C("Max WL Phase: ", dram_info->wl_max_phase, 2); in ddr3_set_performance_params()
492 DEBUG_MAIN_FULL_C("Min WL Phase: ", dram_info->wl_min_phase, 2); in ddr3_set_performance_params()
493 DEBUG_MAIN_FULL_C("Max RL Phase: ", dram_info->rl_max_phase, 2); in ddr3_set_performance_params()
494 DEBUG_MAIN_FULL_C("Min RL Phase: ", dram_info->rl_min_phase, 2); in ddr3_set_performance_params()
496 if (dram_info->wl_max_phase < 2) in ddr3_set_performance_params()
501 trd2rd = 0x1 + (dram_info->rl_max_phase + 1) / 2 + in ddr3_set_performance_params()
502 (dram_info->rl_max_phase + 1) % 2; in ddr3_set_performance_params()
504 tmp1 = (dram_info->rl_max_phase - dram_info->wl_min_phase) / 2 + in ddr3_set_performance_params()
505 (((dram_info->rl_max_phase - dram_info->wl_min_phase) % 2) > in ddr3_set_performance_params()
507 tmp2 = (dram_info->wl_max_phase - dram_info->rl_min_phase) / 2 + in ddr3_set_performance_params()
508 ((dram_info->wl_max_phase - dram_info->rl_min_phase) % 2 > in ddr3_set_performance_params()
621 int ddr3_load_patterns(MV_DRAM_INFO *dram_info, int resume) in ddr3_load_patterns() argument
638 ddr3_load_pbs_patterns(dram_info); in ddr3_load_patterns()
640 ddr3_load_dqs_patterns(dram_info); in ddr3_load_patterns()
667 reg = (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS) | in ddr3_load_patterns()
697 void ddr3_save_training(MV_DRAM_INFO *dram_info) in ddr3_save_training() argument
715 tmp_cs = dram_info->cs_ena; in ddr3_save_training()
720 for (pup = 0; pup < dram_info->num_of_total_pups; in ddr3_save_training()
722 if (pup == dram_info->num_of_std_pups && in ddr3_save_training()
723 dram_info->ecc_ena) in ddr3_save_training()
871 int ddr3_check_if_resume_mode(MV_DRAM_INFO *dram_info, u32 freq) in ddr3_check_if_resume_mode() argument
876 if (dram_info->reg_dimm != 1) { in ddr3_check_if_resume_mode()
881 if (MV_OK != ddr3_write_leveling_hw(freq, dram_info)) { in ddr3_check_if_resume_mode()
887 if (MV_OK != ddr3_load_patterns(dram_info, 1)) { in ddr3_check_if_resume_mode()
893 dram_info->cs_ena = 0x1; in ddr3_check_if_resume_mode()
896 if (MV_OK != ddr3_read_leveling_hw(freq, dram_info)) { in ddr3_check_if_resume_mode()
902 dram_info->cs_ena = ddr3_get_cs_ena_from_reg(); in ddr3_check_if_resume_mode()
915 int ddr3_training_suspend_resume(MV_DRAM_INFO *dram_info) in ddr3_training_suspend_resume() argument
947 freq = dram_info->target_frequency; in ddr3_training_suspend_resume()
949 if (MV_OK != ddr3_dfs_low_2_high(freq, tmp_ratio, dram_info)) { in ddr3_training_suspend_resume()
954 if (dram_info->ecc_ena) { in ddr3_training_suspend_resume()
957 dram_info->num_cs = 1; in ddr3_training_suspend_resume()
958 dram_info->cs_ena = 1; in ddr3_training_suspend_resume()
959 mv_sys_xor_init(dram_info); in ddr3_training_suspend_resume()
1047 int ddr3_get_min_max_rl_phase(MV_DRAM_INFO *dram_info, u32 *min, u32 *max, in ddr3_get_min_max_rl_phase() argument
1055 for (pup = 0; pup < dram_info->num_of_total_pups; pup++) { in ddr3_get_min_max_rl_phase()
1087 int ddr3_odt_read_dynamic_config(MV_DRAM_INFO *dram_info) in ddr3_odt_read_dynamic_config() argument
1104 ddr3_get_min_max_rl_phase(dram_info, &min, &max, cs_max); in ddr3_odt_read_dynamic_config()