Lines Matching refs:sdram_offset
702 u32 *sdram_offset = (u32 *)RESUME_TRAINING_VALUES_ADDR; in ddr3_save_training() local
746 (*sdram_offset) = val; in ddr3_save_training()
747 crc += *sdram_offset; in ddr3_save_training()
748 sdram_offset++; in ddr3_save_training()
757 *sdram_offset = val; in ddr3_save_training()
758 crc += *sdram_offset; in ddr3_save_training()
759 sdram_offset++; in ddr3_save_training()
766 *sdram_offset = reg_read(REG_READ_DATA_SAMPLE_DELAYS_ADDR); in ddr3_save_training()
767 crc += *sdram_offset; in ddr3_save_training()
768 sdram_offset++; in ddr3_save_training()
770 *sdram_offset = reg_read(REG_READ_DATA_READY_DELAYS_ADDR); in ddr3_save_training()
771 crc += *sdram_offset; in ddr3_save_training()
772 sdram_offset++; in ddr3_save_training()
774 sdram_offset = (u32 *)NUM_OF_REGISTER_ADDR; in ddr3_save_training()
775 *sdram_offset = regs; in ddr3_save_training()
779 sdram_offset = (u32 *)CHECKSUM_RESULT_ADDR; in ddr3_save_training()
780 *sdram_offset = crc; in ddr3_save_training()
795 u32 *sdram_offset = (u32 *)RESUME_TRAINING_VALUES_ADDR; in ddr3_read_training_results() local
804 training_val[idx] = *sdram_offset; in ddr3_read_training_results()
805 crc += *sdram_offset; in ddr3_read_training_results()
806 sdram_offset++; in ddr3_read_training_results()
809 sdram_offset = (u32 *)CHECKSUM_RESULT_ADDR; in ddr3_read_training_results()
811 if ((*sdram_offset) == crc) { in ddr3_read_training_results()
874 u32 *sdram_offset = (u32 *)BOOT_INFO_ADDR; in ddr3_check_if_resume_mode() local
904 magic_word = *sdram_offset; in ddr3_check_if_resume_mode()