Lines Matching refs:phase
92 u32 delay, phase, pup, cs; in ddr3_read_leveling_hw() local
109 phase = (reg >> REG_PHY_PHASE_OFFS) & in ddr3_read_leveling_hw()
112 dram_info->rl_val[cs][pup][P] = phase; in ddr3_read_leveling_hw()
113 if (phase > dram_info->rl_max_phase) in ddr3_read_leveling_hw()
114 dram_info->rl_max_phase = phase; in ddr3_read_leveling_hw()
115 if (phase < dram_info->rl_min_phase) in ddr3_read_leveling_hw()
116 dram_info->rl_min_phase = phase; in ddr3_read_leveling_hw()
182 u32 reg, cs, ecc, pup_num, phase, delay, pup; in ddr3_read_leveling_sw() local
291 phase = dram_info->rl_val[cs][pup][P]; in ddr3_read_leveling_sw()
293 ddr3_write_pup_reg(PUP_RL_MODE, cs, pup_num, phase, in ddr3_read_leveling_sw()
339 u32 phase) in overrun() argument
360 info->rl_val[cs][idx][PS] = phase; in overrun()
404 u32 reg, delay, phase, pup, rd_sample_delay, add, locked_pups, in ddr3_read_leveling_single_cs_rl_mode() local
413 phase = 0; in ddr3_read_leveling_single_cs_rl_mode()
434 DEBUG_RL_FULL_D(phase, 1); in ddr3_read_leveling_single_cs_rl_mode()
443 ddr3_write_pup_reg(PUP_RL_MODE, cs, PUP_BC, phase, delay); in ddr3_read_leveling_single_cs_rl_mode()
474 delay, phase); in ddr3_read_leveling_single_cs_rl_mode()
519 if ((!ratio_2to1) && ((phase == 0) || (phase == 4))) in ddr3_read_leveling_single_cs_rl_mode()
532 if ((!ratio_2to1 && phase == in ddr3_read_leveling_single_cs_rl_mode()
534 || (ratio_2to1 && phase == in ddr3_read_leveling_single_cs_rl_mode()
546 if (phase < MAX_PHASE_RL_L_1TO1) { in ddr3_read_leveling_single_cs_rl_mode()
547 if (phase == 1) { in ddr3_read_leveling_single_cs_rl_mode()
548 phase = 4; in ddr3_read_leveling_single_cs_rl_mode()
550 phase++; in ddr3_read_leveling_single_cs_rl_mode()
560 if (phase < MAX_PHASE_RL_UL_1TO1) { in ddr3_read_leveling_single_cs_rl_mode()
561 phase++; in ddr3_read_leveling_single_cs_rl_mode()
565 phase = 0; in ddr3_read_leveling_single_cs_rl_mode()
572 if (phase < MAX_PHASE_RL_L_2TO1) { in ddr3_read_leveling_single_cs_rl_mode()
573 phase++; in ddr3_read_leveling_single_cs_rl_mode()
589 if (phase < MAX_PHASE_RL_UL_2TO1) in ddr3_read_leveling_single_cs_rl_mode()
590 phase++; in ddr3_read_leveling_single_cs_rl_mode()
592 phase = 0; in ddr3_read_leveling_single_cs_rl_mode()
600 if (phase == 0 && first_octet_locked == 0) { in ddr3_read_leveling_single_cs_rl_mode()
636 switch (phase) { in ddr3_read_leveling_single_cs_rl_mode()
662 (phase * in ddr3_read_leveling_single_cs_rl_mode()
756 u32 reg, delay, phase, sum, pup, rd_sample_delay, add, locked_pups, in ddr3_read_leveling_single_cs_window_mode() local
765 phase = 0; in ddr3_read_leveling_single_cs_window_mode()
788 DEBUG_RL_FULL_D(phase, 1); in ddr3_read_leveling_single_cs_window_mode()
797 ddr3_write_pup_reg(PUP_RL_MODE, cs, PUP_BC, phase, delay); in ddr3_read_leveling_single_cs_window_mode()
848 dram_info->rl_val[cs][idx][PE] = phase; in ddr3_read_leveling_single_cs_window_mode()
879 phase; in ddr3_read_leveling_single_cs_window_mode()
956 && phase == MAX_PHASE_RL_L_1TO1) in ddr3_read_leveling_single_cs_window_mode()
958 && phase == in ddr3_read_leveling_single_cs_window_mode()
969 if (phase < MAX_PHASE_RL_L_1TO1) { in ddr3_read_leveling_single_cs_window_mode()
971 if (phase == 0) in ddr3_read_leveling_single_cs_window_mode()
973 if (phase == 1) in ddr3_read_leveling_single_cs_window_mode()
975 phase = 4; in ddr3_read_leveling_single_cs_window_mode()
977 phase++; in ddr3_read_leveling_single_cs_window_mode()
984 if (phase < MAX_PHASE_RL_UL_1TO1) { in ddr3_read_leveling_single_cs_window_mode()
986 if (phase == 0) in ddr3_read_leveling_single_cs_window_mode()
987 phase = 4; in ddr3_read_leveling_single_cs_window_mode()
989 phase++; in ddr3_read_leveling_single_cs_window_mode()
992 phase = 0; in ddr3_read_leveling_single_cs_window_mode()
998 if (phase < MAX_PHASE_RL_L_2TO1) { in ddr3_read_leveling_single_cs_window_mode()
999 phase++; in ddr3_read_leveling_single_cs_window_mode()
1006 if (phase < MAX_PHASE_RL_UL_2TO1) in ddr3_read_leveling_single_cs_window_mode()
1007 phase++; in ddr3_read_leveling_single_cs_window_mode()
1009 phase = 0; in ddr3_read_leveling_single_cs_window_mode()
1018 if (phase == 0 && first_octet_locked == 0) { in ddr3_read_leveling_single_cs_window_mode()
1041 switch (phase) { in ddr3_read_leveling_single_cs_window_mode()
1065 add = (add >> phase * in ddr3_read_leveling_single_cs_window_mode()
1122 phase = tmp / MAX_DELAY_INV; in ddr3_read_leveling_single_cs_window_mode()
1123 if (phase == 1) /* 1:1 mode */ in ddr3_read_leveling_single_cs_window_mode()
1124 phase = 4; in ddr3_read_leveling_single_cs_window_mode()
1126 if (phase < phase_min) /* for the read ready delay */ in ddr3_read_leveling_single_cs_window_mode()
1127 phase_min = phase; in ddr3_read_leveling_single_cs_window_mode()
1129 dram_info->rl_val[cs][idx][P] = phase; in ddr3_read_leveling_single_cs_window_mode()
1139 phase = tmp / MAX_DELAY; in ddr3_read_leveling_single_cs_window_mode()
1141 if (phase < phase_min) /* for the read ready delay */ in ddr3_read_leveling_single_cs_window_mode()
1142 phase_min = phase; in ddr3_read_leveling_single_cs_window_mode()
1144 dram_info->rl_val[cs][idx][P] = phase; in ddr3_read_leveling_single_cs_window_mode()
1161 phase = tmp / MAX_DELAY; in ddr3_read_leveling_single_cs_window_mode()
1162 if (!ratio_2to1 && phase > 1) /* 1:1 mode */ in ddr3_read_leveling_single_cs_window_mode()
1163 phase += 2; in ddr3_read_leveling_single_cs_window_mode()
1165 if (phase < phase_min) /* for the read ready delay */ in ddr3_read_leveling_single_cs_window_mode()
1166 phase_min = phase; in ddr3_read_leveling_single_cs_window_mode()
1168 dram_info->rl_val[cs][idx][P] = phase; in ddr3_read_leveling_single_cs_window_mode()