Lines Matching refs:pup
92 u32 delay, phase, pup, cs; in ddr3_read_leveling_hw() local
100 for (pup = 0; in ddr3_read_leveling_hw()
101 pup < dram_info->num_of_total_pups; in ddr3_read_leveling_hw()
102 pup++) { in ddr3_read_leveling_hw()
103 if (pup == dram_info->num_of_std_pups in ddr3_read_leveling_hw()
105 pup = ECC_PUP; in ddr3_read_leveling_hw()
108 pup); in ddr3_read_leveling_hw()
112 dram_info->rl_val[cs][pup][P] = phase; in ddr3_read_leveling_hw()
117 dram_info->rl_val[cs][pup][D] = delay; in ddr3_read_leveling_hw()
118 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
122 cs, pup); in ddr3_read_leveling_hw()
123 dram_info->rl_val[cs][pup][DQS] = in ddr3_read_leveling_hw()
131 for (pup = 0; in ddr3_read_leveling_hw()
132 pup < (dram_info->num_of_total_pups); in ddr3_read_leveling_hw()
133 pup++) { in ddr3_read_leveling_hw()
134 if (pup == dram_info->num_of_std_pups in ddr3_read_leveling_hw()
136 pup = ECC_PUP; in ddr3_read_leveling_hw()
138 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_hw()
141 rl_val[cs][pup][P], 1); in ddr3_read_leveling_hw()
144 rl_val[cs][pup][D], 2); in ddr3_read_leveling_hw()
182 u32 reg, cs, ecc, pup_num, phase, delay, pup; in ddr3_read_leveling_sw() local
266 for (pup = 0; in ddr3_read_leveling_sw()
267 pup < (dram_info->num_of_std_pups + dram_info->ecc_ena); in ddr3_read_leveling_sw()
268 pup++) { in ddr3_read_leveling_sw()
270 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_sw()
272 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][P], 1); in ddr3_read_leveling_sw()
274 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][D], 2); in ddr3_read_leveling_sw()
284 for (pup = 0; in ddr3_read_leveling_sw()
285 pup < (dram_info->num_of_std_pups + dram_info->ecc_ena); in ddr3_read_leveling_sw()
286 pup++) { in ddr3_read_leveling_sw()
288 pup_num = (pup == dram_info->num_of_std_pups) ? ECC_BIT : pup; in ddr3_read_leveling_sw()
291 phase = dram_info->rl_val[cs][pup][P]; in ddr3_read_leveling_sw()
292 delay = dram_info->rl_val[cs][pup][D]; in ddr3_read_leveling_sw()
336 static void overrun(u32 cs, MV_DRAM_INFO *info, u32 pup, u32 locked_pups, in overrun() argument
342 if (((~locked_pups >> pup) & 0x1) && (final_delay == 0)) { in overrun()
345 idx = pup + ecc * ECC_BIT; in overrun()
353 (u32)pup, 1); in overrun()
366 (u32)pup, 1); in overrun()
373 (u32)pup, 1); in overrun()
404 u32 reg, delay, phase, pup, rd_sample_delay, add, locked_pups, in ddr3_read_leveling_single_cs_rl_mode() local
421 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); in ddr3_read_leveling_single_cs_rl_mode()
422 pup++) in ddr3_read_leveling_single_cs_rl_mode()
423 dram_info->rl_val[cs][pup + ecc * ECC_BIT][S] = 0; in ddr3_read_leveling_single_cs_rl_mode()
467 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); pup++) { in ddr3_read_leveling_single_cs_rl_mode()
470 (REG_DRAM_TRAINING_2_OVERRUN_OFFS + pup)) & 0x1)) { in ddr3_read_leveling_single_cs_rl_mode()
471 overrun(cs, dram_info, pup, locked_pups, in ddr3_read_leveling_single_cs_rl_mode()
477 (u32)pup, 1); in ddr3_read_leveling_single_cs_rl_mode()
515 idx = pup + ecc * ECC_BIT; in ddr3_read_leveling_single_cs_rl_mode()
577 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); pup++) { in ddr3_read_leveling_single_cs_rl_mode()
582 pup, 1); in ddr3_read_leveling_single_cs_rl_mode()
605 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); pup++) { in ddr3_read_leveling_single_cs_rl_mode()
610 pup, 1); in ddr3_read_leveling_single_cs_rl_mode()
678 for (pup = 0; pup < in ddr3_read_leveling_single_cs_rl_mode()
680 pup++) { in ddr3_read_leveling_single_cs_rl_mode()
689 for (pup = 0; pup < (dram_info->num_of_std_pups); pup++) { in ddr3_read_leveling_single_cs_rl_mode()
690 if (dram_info->rl_val[cs][pup][PS] < phase_min) in ddr3_read_leveling_single_cs_rl_mode()
691 phase_min = dram_info->rl_val[cs][pup][PS]; in ddr3_read_leveling_single_cs_rl_mode()
731 for (pup = 0; pup < dram_info->num_of_total_pups; pup++) { in ddr3_read_leveling_single_cs_rl_mode()
732 reg = ddr3_read_pup_reg(PUP_RL_MODE + 0x1, cs, pup); in ddr3_read_leveling_single_cs_rl_mode()
733 dram_info->rl_val[cs][pup][DQS] = (reg & 0x3F); in ddr3_read_leveling_single_cs_rl_mode()
756 u32 reg, delay, phase, sum, pup, rd_sample_delay, add, locked_pups, in ddr3_read_leveling_single_cs_window_mode() local
775 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); in ddr3_read_leveling_single_cs_window_mode()
776 pup++) in ddr3_read_leveling_single_cs_window_mode()
777 dram_info->rl_val[cs][pup + ecc * ECC_BIT][S] = 0; in ddr3_read_leveling_single_cs_window_mode()
820 for (pup = 0; pup < (dram_info->num_of_std_pups * in ddr3_read_leveling_single_cs_window_mode()
821 (1 - ecc) + ecc); pup++) { in ddr3_read_leveling_single_cs_window_mode()
825 idx = pup + ecc * ECC_BIT; in ddr3_read_leveling_single_cs_window_mode()
830 pup)) & 0x1)) { in ddr3_read_leveling_single_cs_window_mode()
839 if (((~locked_pups >> pup) & 0x1) in ddr3_read_leveling_single_cs_window_mode()
843 (u32)pup, 1); in ddr3_read_leveling_single_cs_window_mode()
853 (u32)pup, 1); in ddr3_read_leveling_single_cs_window_mode()
866 if (((~locked_pups >> pup) & 0x1)) { in ddr3_read_leveling_single_cs_window_mode()
869 (u32)pup, 1); in ddr3_read_leveling_single_cs_window_mode()
887 (u32)pup, 1); in ddr3_read_leveling_single_cs_window_mode()
904 (u32)pup, 1); in ddr3_read_leveling_single_cs_window_mode()
1080 for (pup = 0; in ddr3_read_leveling_single_cs_window_mode()
1081 pup < in ddr3_read_leveling_single_cs_window_mode()
1083 pup++) { in ddr3_read_leveling_single_cs_window_mode()
1092 for (pup = 0; pup < (dram_info->num_of_std_pups); pup++) { in ddr3_read_leveling_single_cs_window_mode()
1094 DEBUG_RL_D((u32) pup, 1); in ddr3_read_leveling_single_cs_window_mode()
1096 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][PS], 1); in ddr3_read_leveling_single_cs_window_mode()
1098 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][DS], 2); in ddr3_read_leveling_single_cs_window_mode()
1100 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][PE], 1); in ddr3_read_leveling_single_cs_window_mode()
1102 DEBUG_RL_D((u32) dram_info->rl_val[cs][pup][DE], 2); in ddr3_read_leveling_single_cs_window_mode()
1107 for (pup = 0; pup < (dram_info->num_of_std_pups * (1 - ecc) + ecc); in ddr3_read_leveling_single_cs_window_mode()
1108 pup++) { in ddr3_read_leveling_single_cs_window_mode()
1206 for (pup = 0; pup < dram_info->num_of_total_pups; pup++) { in ddr3_read_leveling_single_cs_window_mode()
1207 reg = ddr3_read_pup_reg(PUP_RL_MODE + 0x1, cs, pup); in ddr3_read_leveling_single_cs_window_mode()
1208 dram_info->rl_val[cs][pup][DQS] = (reg & 0x3F); in ddr3_read_leveling_single_cs_window_mode()