Lines Matching refs:var
140 u32 var; in xenon_mmc_phy_init() local
143 var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_init()
144 var |= SAMPL_INV_QSP_PHASE_SELECT; in xenon_mmc_phy_init()
150 var |= EMMC_PHY_SLOW_MODE; in xenon_mmc_phy_init()
151 sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_init()
157 var = sdhci_readl(host, SDHCI_CLOCK_CONTROL); in xenon_mmc_phy_init()
158 if (var & SDHCI_CLOCK_INT_STABLE) in xenon_mmc_phy_init()
170 var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_init()
171 var |= PHY_INITIALIZAION; in xenon_mmc_phy_init()
172 sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_init()
183 var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_init()
184 var &= PHY_INITIALIZAION; in xenon_mmc_phy_init()
185 if (!var) in xenon_mmc_phy_init()
261 u32 var; in xenon_mmc_phy_set() local
264 var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL); in xenon_mmc_phy_set()
265 var |= AUTO_RECEN_CTRL | OEN_QSN | FC_QSP_RECEN | in xenon_mmc_phy_set()
267 sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL); in xenon_mmc_phy_set()
270 var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL1); in xenon_mmc_phy_set()
271 var |= (EMMC5_1_FC_CMD_PU | EMMC5_1_FC_DQ_PU); in xenon_mmc_phy_set()
272 var &= ~(EMMC5_1_FC_CMD_PD | EMMC5_1_FC_DQ_PD); in xenon_mmc_phy_set()
273 sdhci_writel(host, var, EMMC_PHY_PAD_CONTROL1); in xenon_mmc_phy_set()
286 var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_set()
287 var |= OUTPUT_QSN_PHASE_SELECT; in xenon_mmc_phy_set()
288 sdhci_writel(host, var, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_set()
295 var = sdhci_readl(host, SDHCI_CLOCK_CONTROL); in xenon_mmc_phy_set()
296 var &= ~SDHCI_CLOCK_CARD_EN; in xenon_mmc_phy_set()
297 sdhci_writew(host, var, SDHCI_CLOCK_CONTROL); in xenon_mmc_phy_set()
299 var = sdhci_readl(host, EMMC_PHY_FUNC_CONTROL); in xenon_mmc_phy_set()
301 var |= (DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) | CMD_DDR_MODE; in xenon_mmc_phy_set()
303 var &= ~((DQ_DDR_MODE_MASK << DQ_DDR_MODE_SHIFT) | in xenon_mmc_phy_set()
306 sdhci_writel(host, var, EMMC_PHY_FUNC_CONTROL); in xenon_mmc_phy_set()
309 var = sdhci_readl(host, SDHCI_CLOCK_CONTROL); in xenon_mmc_phy_set()
310 var |= SDHCI_CLOCK_CARD_EN; in xenon_mmc_phy_set()
311 sdhci_writew(host, var, SDHCI_CLOCK_CONTROL); in xenon_mmc_phy_set()
319 u32 var; in xenon_mmc_set_acg() local
321 var = sdhci_readl(host, SDHC_SYS_OP_CTRL); in xenon_mmc_set_acg()
323 var &= ~AUTO_CLKGATE_DISABLE_MASK; in xenon_mmc_set_acg()
325 var |= AUTO_CLKGATE_DISABLE_MASK; in xenon_mmc_set_acg()
327 sdhci_writel(host, var, SDHC_SYS_OP_CTRL); in xenon_mmc_set_acg()
335 u32 var; in xenon_mmc_enable_slot() local
337 var = sdhci_readl(host, SDHC_SYS_OP_CTRL); in xenon_mmc_enable_slot()
338 var |= SLOT_MASK(slot) << SLOT_ENABLE_SHIFT; in xenon_mmc_enable_slot()
339 sdhci_writel(host, var, SDHC_SYS_OP_CTRL); in xenon_mmc_enable_slot()
345 u32 var; in xenon_mmc_disable_slot() local
347 var = sdhci_readl(host, SDHC_SYS_OP_CTRL); in xenon_mmc_disable_slot()
348 var &= ~(SLOT_MASK(slot) << SLOT_ENABLE_SHIFT); in xenon_mmc_disable_slot()
349 sdhci_writel(host, var, SDHC_SYS_OP_CTRL); in xenon_mmc_disable_slot()
355 u32 var; in xenon_mmc_enable_parallel_tran() local
357 var = sdhci_readl(host, SDHC_SYS_EXT_OP_CTRL); in xenon_mmc_enable_parallel_tran()
358 var |= SLOT_MASK(slot); in xenon_mmc_enable_parallel_tran()
359 sdhci_writel(host, var, SDHC_SYS_EXT_OP_CTRL); in xenon_mmc_enable_parallel_tran()
364 u32 var; in xenon_mmc_disable_tuning() local
367 var = sdhci_readl(host, SDHC_SLOT_RETUNING_REQ_CTRL); in xenon_mmc_disable_tuning()
368 var &= ~RETUNING_COMPATIBLE; in xenon_mmc_disable_tuning()
369 sdhci_writel(host, var, SDHC_SLOT_RETUNING_REQ_CTRL); in xenon_mmc_disable_tuning()
372 var = sdhci_readl(host, SDHCI_SIGNAL_ENABLE); in xenon_mmc_disable_tuning()
373 var &= ~SDHCI_RETUNE_EVT_INTSIG; in xenon_mmc_disable_tuning()
374 sdhci_writel(host, var, SDHCI_SIGNAL_ENABLE); in xenon_mmc_disable_tuning()