Lines Matching refs:lbc
161 fsl_lbc_t *lbc = ctrl->regs; in set_addr() local
167 out_be32(&lbc->fbar, page_addr >> 6); in set_addr()
168 out_be32(&lbc->fpar, in set_addr()
173 out_be32(&lbc->fbar, page_addr >> 5); in set_addr()
174 out_be32(&lbc->fpar, in set_addr()
201 fsl_lbc_t *lbc = ctrl->regs; in fsl_elbc_run_command() local
207 out_be32(&lbc->fmr, priv->fmr | 3); in fsl_elbc_run_command()
209 out_be32(&lbc->mdr, ctrl->mdr); in fsl_elbc_run_command()
212 in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr)); in fsl_elbc_run_command()
215 in_be32(&lbc->fbar), in_be32(&lbc->fpar), in fsl_elbc_run_command()
216 in_be32(&lbc->fbcr), priv->bank); in fsl_elbc_run_command()
219 out_be32(&lbc->lsor, priv->bank); in fsl_elbc_run_command()
226 ltesr = in_be32(&lbc->ltesr); in fsl_elbc_run_command()
232 out_be32(&lbc->ltesr, ctrl->status); in fsl_elbc_run_command()
233 out_be32(&lbc->lteatr, 0); in fsl_elbc_run_command()
237 ctrl->mdr = in_be32(&lbc->mdr); in fsl_elbc_run_command()
242 ctrl->status, ctrl->mdr, in_be32(&lbc->fmr)); in fsl_elbc_run_command()
252 fsl_lbc_t *lbc = ctrl->regs; in fsl_elbc_do_read() local
255 out_be32(&lbc->fir, in fsl_elbc_do_read()
262 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | in fsl_elbc_do_read()
265 out_be32(&lbc->fir, in fsl_elbc_do_read()
272 out_be32(&lbc->fcr, in fsl_elbc_do_read()
275 out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT); in fsl_elbc_do_read()
286 fsl_lbc_t *lbc = ctrl->regs; in fsl_elbc_cmdfunc() local
305 out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */ in fsl_elbc_cmdfunc()
320 out_be32(&lbc->fbcr, mtd->oobsize - column); in fsl_elbc_cmdfunc()
335 out_be32(&lbc->fir, (FIR_OP_CW0 << FIR_OP0_SHIFT) | in fsl_elbc_cmdfunc()
338 out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT); in fsl_elbc_cmdfunc()
343 out_be32(&lbc->fbcr, 256); in fsl_elbc_cmdfunc()
362 out_be32(&lbc->fir, in fsl_elbc_cmdfunc()
367 out_be32(&lbc->fcr, in fsl_elbc_cmdfunc()
371 out_be32(&lbc->fbcr, 0); in fsl_elbc_cmdfunc()
391 out_be32(&lbc->fir, in fsl_elbc_cmdfunc()
401 out_be32(&lbc->fir, in fsl_elbc_cmdfunc()
423 out_be32(&lbc->fcr, fcr); in fsl_elbc_cmdfunc()
439 out_be32(&lbc->fbcr, ctrl->index); in fsl_elbc_cmdfunc()
441 out_be32(&lbc->fbcr, 0); in fsl_elbc_cmdfunc()
451 out_be32(&lbc->fir, in fsl_elbc_cmdfunc()
454 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT); in fsl_elbc_cmdfunc()
455 out_be32(&lbc->fbcr, 1); in fsl_elbc_cmdfunc()
470 out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT); in fsl_elbc_cmdfunc()
471 out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT); in fsl_elbc_cmdfunc()
572 fsl_lbc_t *lbc = ctrl->regs; in fsl_elbc_wait() local
579 out_be32(&lbc->fir, in fsl_elbc_wait()
582 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT); in fsl_elbc_wait()
583 out_be32(&lbc->fbcr, 1); in fsl_elbc_wait()