Lines Matching refs:timings
1232 const struct nand_sdr_timings *timings) in sunxi_nand_chip_set_timings() argument
1238 if (timings->tCLS_min > min_clk_period) in sunxi_nand_chip_set_timings()
1239 min_clk_period = timings->tCLS_min; in sunxi_nand_chip_set_timings()
1242 if (timings->tCLH_min > min_clk_period) in sunxi_nand_chip_set_timings()
1243 min_clk_period = timings->tCLH_min; in sunxi_nand_chip_set_timings()
1246 if (timings->tCS_min > min_clk_period) in sunxi_nand_chip_set_timings()
1247 min_clk_period = timings->tCS_min; in sunxi_nand_chip_set_timings()
1250 if (timings->tCH_min > min_clk_period) in sunxi_nand_chip_set_timings()
1251 min_clk_period = timings->tCH_min; in sunxi_nand_chip_set_timings()
1254 if (timings->tWP_min > min_clk_period) in sunxi_nand_chip_set_timings()
1255 min_clk_period = timings->tWP_min; in sunxi_nand_chip_set_timings()
1258 if (timings->tWH_min > min_clk_period) in sunxi_nand_chip_set_timings()
1259 min_clk_period = timings->tWH_min; in sunxi_nand_chip_set_timings()
1262 if (timings->tALS_min > min_clk_period) in sunxi_nand_chip_set_timings()
1263 min_clk_period = timings->tALS_min; in sunxi_nand_chip_set_timings()
1266 if (timings->tDS_min > min_clk_period) in sunxi_nand_chip_set_timings()
1267 min_clk_period = timings->tDS_min; in sunxi_nand_chip_set_timings()
1270 if (timings->tDH_min > min_clk_period) in sunxi_nand_chip_set_timings()
1271 min_clk_period = timings->tDH_min; in sunxi_nand_chip_set_timings()
1274 if (timings->tRR_min > (min_clk_period * 3)) in sunxi_nand_chip_set_timings()
1275 min_clk_period = DIV_ROUND_UP(timings->tRR_min, 3); in sunxi_nand_chip_set_timings()
1278 if (timings->tALH_min > min_clk_period) in sunxi_nand_chip_set_timings()
1279 min_clk_period = timings->tALH_min; in sunxi_nand_chip_set_timings()
1282 if (timings->tRP_min > min_clk_period) in sunxi_nand_chip_set_timings()
1283 min_clk_period = timings->tRP_min; in sunxi_nand_chip_set_timings()
1286 if (timings->tREH_min > min_clk_period) in sunxi_nand_chip_set_timings()
1287 min_clk_period = timings->tREH_min; in sunxi_nand_chip_set_timings()
1290 if (timings->tRC_min > (min_clk_period * 2)) in sunxi_nand_chip_set_timings()
1291 min_clk_period = DIV_ROUND_UP(timings->tRC_min, 2); in sunxi_nand_chip_set_timings()
1294 if (timings->tWC_min > (min_clk_period * 2)) in sunxi_nand_chip_set_timings()
1295 min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2); in sunxi_nand_chip_set_timings()
1298 tWB = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max, in sunxi_nand_chip_set_timings()
1305 tADL = DIV_ROUND_UP(timings->tADL_min, min_clk_period) >> 3; in sunxi_nand_chip_set_timings()
1311 tWHR = DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3; in sunxi_nand_chip_set_timings()
1317 tRHW = sunxi_nand_lookup_timing(tRHW_lut, timings->tRHW_min, in sunxi_nand_chip_set_timings()
1338 chip->timing_ctl = (timings->tRC_min < 30000) ? NFC_TIMING_CTL_EDO : 0; in sunxi_nand_chip_set_timings()
1358 const struct nand_sdr_timings *timings; in sunxi_nand_chip_init_timings() local
1386 timings = onfi_async_timing_mode_to_sdr_timings(mode); in sunxi_nand_chip_init_timings()
1387 if (IS_ERR(timings)) in sunxi_nand_chip_init_timings()
1388 return PTR_ERR(timings); in sunxi_nand_chip_init_timings()
1390 return sunxi_nand_chip_set_timings(nfc, chip, timings); in sunxi_nand_chip_init_timings()
1610 const struct nand_sdr_timings *timings; in sunxi_nand_chip_init() local
1690 timings = onfi_async_timing_mode_to_sdr_timings(0); in sunxi_nand_chip_init()
1691 if (IS_ERR(timings)) { in sunxi_nand_chip_init()
1692 ret = PTR_ERR(timings); in sunxi_nand_chip_init()
1699 ret = sunxi_nand_chip_set_timings(nfc, chip, timings); in sunxi_nand_chip_init()