Lines Matching refs:priv
275 static void pdma_write(struct mt7620_eth_priv *priv, u32 reg, u32 val) in pdma_write() argument
277 writel(val, priv->fe_base + PDMA_BASE + reg); in pdma_write()
280 static void gdma_write(struct mt7620_eth_priv *priv, u32 reg, u32 val) in gdma_write() argument
282 writel(val, priv->fe_base + GDMA_BASE + reg); in gdma_write()
285 static void gdma_rmw(struct mt7620_eth_priv *priv, u32 reg, u32 clr, u32 set) in gdma_rmw() argument
287 clrsetbits_le32(priv->fe_base + GDMA_BASE + reg, clr, set); in gdma_rmw()
290 static u32 gsw_read(struct mt7620_eth_priv *priv, u32 reg) in gsw_read() argument
292 return readl(priv->gsw_base + reg); in gsw_read()
295 static void gsw_write(struct mt7620_eth_priv *priv, u32 reg, u32 val) in gsw_write() argument
297 writel(val, priv->gsw_base + reg); in gsw_write()
300 static void gsw_rmw(struct mt7620_eth_priv *priv, u32 reg, u32 clr, u32 set) in gsw_rmw() argument
302 clrsetbits_le32(priv->gsw_base + reg, clr, set); in gsw_rmw()
305 static int mt7620_mdio_rw(struct mt7620_eth_priv *priv, u32 phy, u32 reg, in mt7620_mdio_rw() argument
318 gsw_write(priv, GSW_PIAC, val); in mt7620_mdio_rw()
319 gsw_write(priv, GSW_PIAC, val | PHY_ACS_ST); in mt7620_mdio_rw()
321 ret = readl_poll_timeout(priv->gsw_base + GSW_PIAC, val, in mt7620_mdio_rw()
324 dev_err(priv->dev, "mt7620_eth: MDIO access timeout\n"); in mt7620_mdio_rw()
329 val = gsw_read(priv, GSW_PIAC); in mt7620_mdio_rw()
336 static int mt7620_mii_read(struct mt7620_eth_priv *priv, u32 phy, u32 reg) in mt7620_mii_read() argument
338 return mt7620_mdio_rw(priv, phy, reg, 0, MDIO_CMD_READ); in mt7620_mii_read()
341 static int mt7620_mii_write(struct mt7620_eth_priv *priv, u32 phy, u32 reg, in mt7620_mii_write() argument
344 return mt7620_mdio_rw(priv, phy, reg, val, MDIO_CMD_WRITE); in mt7620_mii_write()
349 struct mt7620_eth_priv *priv = bus->priv; in mt7620_mdio_read() local
353 return mt7620_mdio_rw(priv, addr, reg, 0, MDIO_CMD_READ); in mt7620_mdio_read()
355 ret = mt7620_mdio_rw(priv, addr, MII_MMD_ACC_CTL_REG, in mt7620_mdio_read()
361 ret = mt7620_mdio_rw(priv, addr, MII_MMD_ADDR_DATA_REG, reg, in mt7620_mdio_read()
366 ret = mt7620_mdio_rw(priv, addr, MII_MMD_ACC_CTL_REG, in mt7620_mdio_read()
372 return mt7620_mdio_rw(priv, addr, MII_MMD_ADDR_DATA_REG, 0, in mt7620_mdio_read()
379 struct mt7620_eth_priv *priv = bus->priv; in mt7620_mdio_write() local
383 return mt7620_mdio_rw(priv, addr, reg, val, MDIO_CMD_WRITE); in mt7620_mdio_write()
385 ret = mt7620_mdio_rw(priv, addr, MII_MMD_ACC_CTL_REG, in mt7620_mdio_write()
391 ret = mt7620_mdio_rw(priv, addr, MII_MMD_ADDR_DATA_REG, reg, in mt7620_mdio_write()
396 ret = mt7620_mdio_rw(priv, addr, MII_MMD_ACC_CTL_REG, in mt7620_mdio_write()
402 return mt7620_mdio_rw(priv, addr, MII_MMD_ADDR_DATA_REG, val, in mt7620_mdio_write()
408 struct mt7620_eth_priv *priv = dev_get_priv(dev); in mt7620_mdio_register() local
419 mdio_bus->priv = (void *)priv; in mt7620_mdio_register()
426 priv->mdio_bus = mdio_bus; in mt7620_mdio_register()
431 static int mt7530_reg_read(struct mt7620_eth_priv *priv, u32 reg, u32 *data) in mt7530_reg_read() argument
436 ret = mt7620_mii_write(priv, 0x1f, 0x1f, in mt7530_reg_read()
442 low_word = mt7620_mii_read(priv, 0x1f, FIELD_GET(MT7530_REG_ADDR, reg)); in mt7530_reg_read()
447 high_word = mt7620_mii_read(priv, 0x1f, 0x10); in mt7530_reg_read()
457 static int mt7530_reg_write(struct mt7620_eth_priv *priv, u32 reg, u32 data) in mt7530_reg_write() argument
462 ret = mt7620_mii_write(priv, 0x1f, 0x1f, in mt7530_reg_write()
468 ret = mt7620_mii_write(priv, 0x1f, FIELD_GET(MT7530_REG_ADDR, reg), in mt7530_reg_write()
474 return mt7620_mii_write(priv, 0x1f, 0x10, data >> 16); in mt7530_reg_write()
477 static void mt7620_phy_restart_an(struct mt7620_eth_priv *priv, u32 phy) in mt7620_phy_restart_an() argument
481 val = mt7620_mii_read(priv, phy, MII_BMCR); in mt7620_phy_restart_an()
483 mt7620_mii_write(priv, phy, MII_BMCR, val); in mt7620_phy_restart_an()
486 static void mt7620_gsw_ephy_init(struct mt7620_eth_priv *priv) in mt7620_gsw_ephy_init() argument
492 ret = misc_ioctl(priv->sysc, MT7620_SYSC_IOCTL_GET_CHIP_REV, &chip_rev); in mt7620_gsw_ephy_init()
495 dev_warn(priv->dev, "mt7620_eth: failed to get chip rev\n"); in mt7620_gsw_ephy_init()
500 mt7620_mii_write(priv, 1, 31, 0x4000); in mt7620_gsw_ephy_init()
501 mt7620_mii_write(priv, 1, 17, 0x7444); in mt7620_gsw_ephy_init()
504 mt7620_mii_write(priv, 1, 19, 0x0114); in mt7620_gsw_ephy_init()
506 mt7620_mii_write(priv, 1, 19, 0x0117); in mt7620_gsw_ephy_init()
508 mt7620_mii_write(priv, 1, 22, 0x10cf); in mt7620_gsw_ephy_init()
509 mt7620_mii_write(priv, 1, 25, 0x6212); in mt7620_gsw_ephy_init()
510 mt7620_mii_write(priv, 1, 26, 0x0777); in mt7620_gsw_ephy_init()
511 mt7620_mii_write(priv, 1, 29, 0x4000); in mt7620_gsw_ephy_init()
512 mt7620_mii_write(priv, 1, 28, 0xc077); in mt7620_gsw_ephy_init()
513 mt7620_mii_write(priv, 1, 24, 0x0000); in mt7620_gsw_ephy_init()
516 mt7620_mii_write(priv, 1, 31, 0x3000); in mt7620_gsw_ephy_init()
517 mt7620_mii_write(priv, 1, 17, 0x4838); in mt7620_gsw_ephy_init()
520 mt7620_mii_write(priv, 1, 31, 0x2000); in mt7620_gsw_ephy_init()
523 mt7620_mii_write(priv, 1, 21, 0x0515); in mt7620_gsw_ephy_init()
524 mt7620_mii_write(priv, 1, 22, 0x0053); in mt7620_gsw_ephy_init()
525 mt7620_mii_write(priv, 1, 23, 0x00bf); in mt7620_gsw_ephy_init()
526 mt7620_mii_write(priv, 1, 24, 0x0aaf); in mt7620_gsw_ephy_init()
527 mt7620_mii_write(priv, 1, 25, 0x0fad); in mt7620_gsw_ephy_init()
528 mt7620_mii_write(priv, 1, 26, 0x0fc1); in mt7620_gsw_ephy_init()
530 mt7620_mii_write(priv, 1, 21, 0x0517); in mt7620_gsw_ephy_init()
531 mt7620_mii_write(priv, 1, 22, 0x0fd2); in mt7620_gsw_ephy_init()
532 mt7620_mii_write(priv, 1, 23, 0x00bf); in mt7620_gsw_ephy_init()
533 mt7620_mii_write(priv, 1, 24, 0x0aab); in mt7620_gsw_ephy_init()
534 mt7620_mii_write(priv, 1, 25, 0x00ae); in mt7620_gsw_ephy_init()
535 mt7620_mii_write(priv, 1, 26, 0x0fff); in mt7620_gsw_ephy_init()
539 mt7620_mii_write(priv, 1, 31, 0x1000); in mt7620_gsw_ephy_init()
540 mt7620_mii_write(priv, 1, 17, 0xe7f8); in mt7620_gsw_ephy_init()
543 mt7620_mii_write(priv, 1, 31, 0x8000); in mt7620_gsw_ephy_init()
544 for (i = 0; i < priv->ephy_num; i++) in mt7620_gsw_ephy_init()
545 mt7620_mii_write(priv, i, 30, 0xa000); in mt7620_gsw_ephy_init()
547 for (i = 0; i < priv->ephy_num; i++) in mt7620_gsw_ephy_init()
548 mt7620_mii_write(priv, i, 4, 0x05e1); in mt7620_gsw_ephy_init()
551 mt7620_mii_write(priv, 1, 31, 0xa000); in mt7620_gsw_ephy_init()
552 mt7620_mii_write(priv, 0, 16, 0x1111); in mt7620_gsw_ephy_init()
553 mt7620_mii_write(priv, 1, 16, 0x1010); in mt7620_gsw_ephy_init()
554 mt7620_mii_write(priv, 2, 16, 0x1515); in mt7620_gsw_ephy_init()
555 mt7620_mii_write(priv, 3, 16, 0x0f0f); in mt7620_gsw_ephy_init()
556 if (priv->ephy_num == NUM_FE_PHYS) in mt7620_gsw_ephy_init()
557 mt7620_mii_write(priv, 4, 16, 0x1313); in mt7620_gsw_ephy_init()
560 for (i = 0; i < priv->ephy_num; i++) in mt7620_gsw_ephy_init()
561 mt7620_phy_restart_an(priv, i); in mt7620_gsw_ephy_init()
563 if (priv->port_cfg[0].phy_addr > 0) in mt7620_gsw_ephy_init()
564 mt7620_phy_restart_an(priv, priv->port_cfg[0].phy_addr); in mt7620_gsw_ephy_init()
566 if (priv->port_cfg[1].phy_addr > 0) in mt7620_gsw_ephy_init()
567 mt7620_phy_restart_an(priv, priv->port_cfg[1].phy_addr); in mt7620_gsw_ephy_init()
570 static int mt7620_setup_gmac_mode(struct mt7620_eth_priv *priv, u32 gmac, in mt7620_setup_gmac_mode() argument
610 ret = misc_ioctl(priv->sysc, req, &ge_mode); in mt7620_setup_gmac_mode()
612 dev_warn(priv->dev, "mt7620_eth: failed to set GE%u mode\n", in mt7620_setup_gmac_mode()
618 static void mt7620_gsw_setup_port(struct mt7620_eth_priv *priv, u32 port, in mt7620_gsw_setup_port() argument
625 gsw_write(priv, GSW_PMCR(port), FORCE_MODE); in mt7620_gsw_setup_port()
643 gsw_write(priv, GSW_PMCR(port), pmcr); in mt7620_gsw_setup_port()
646 static void mt7620_gsw_set_port_isolation(struct mt7620_eth_priv *priv) in mt7620_gsw_set_port_isolation() argument
653 gsw_write(priv, GSW_PCR(i), in mt7620_gsw_set_port_isolation()
656 gsw_write(priv, GSW_PCR(i), in mt7620_gsw_set_port_isolation()
660 gsw_write(priv, GSW_PVC(i), FIELD_PREP(STAG_VPID, 0x8100) | in mt7620_gsw_set_port_isolation()
665 static void mt7620_gsw_setup_phy_polling(struct mt7620_eth_priv *priv) in mt7620_gsw_setup_phy_polling() argument
669 if (priv->port_cfg[0].mode == PHY_INTERFACE_MODE_NONE) in mt7620_gsw_setup_phy_polling()
670 priv->ephy_num = NUM_FE_PHYS; in mt7620_gsw_setup_phy_polling()
672 priv->ephy_num = NUM_FE_PHYS - 1; in mt7620_gsw_setup_phy_polling()
674 if (priv->port_cfg[0].phy_addr < 0 && priv->port_cfg[1].phy_addr < 0) in mt7620_gsw_setup_phy_polling()
677 if (priv->port_cfg[0].phy_addr > 0 && priv->port_cfg[1].phy_addr > 0) { in mt7620_gsw_setup_phy_polling()
678 phy_addr_st = priv->port_cfg[0].phy_addr; in mt7620_gsw_setup_phy_polling()
679 phy_addr_end = priv->port_cfg[1].phy_addr; in mt7620_gsw_setup_phy_polling()
680 } else if (priv->port_cfg[0].phy_addr > 0) { in mt7620_gsw_setup_phy_polling()
681 phy_addr_st = priv->port_cfg[0].phy_addr; in mt7620_gsw_setup_phy_polling()
682 phy_addr_end = priv->port_cfg[0].phy_addr + 1; in mt7620_gsw_setup_phy_polling()
685 phy_addr_end = priv->port_cfg[1].phy_addr; in mt7620_gsw_setup_phy_polling()
688 gsw_rmw(priv, GSW_PPSC, PHY_AP_END_ADDR | PHY_AP_START_ADDR, in mt7620_gsw_setup_phy_polling()
693 static void mt7530_gsw_set_port_isolation(struct mt7620_eth_priv *priv) in mt7530_gsw_set_port_isolation() argument
700 mt7530_reg_write(priv, GSW_PCR(i), in mt7530_gsw_set_port_isolation()
703 mt7530_reg_write(priv, GSW_PCR(i), in mt7530_gsw_set_port_isolation()
707 mt7530_reg_write(priv, GSW_PVC(i), in mt7530_gsw_set_port_isolation()
713 static void mt7620_gsw_config_mt7530(struct mt7620_eth_priv *priv) in mt7620_gsw_config_mt7530() argument
719 gsw_write(priv, GSW_GPC1, PHY_DIS | FIELD_PREP(PHY_BASE, 12) | in mt7620_gsw_config_mt7530()
723 dm_gpio_set_value(&priv->gpio_swrst, 1); in mt7620_gsw_config_mt7530()
728 phy_val = mt7620_mii_read(priv, i, MII_BMCR); in mt7620_gsw_config_mt7530()
730 mt7620_mii_write(priv, i, MII_BMCR, phy_val); in mt7620_gsw_config_mt7530()
734 mt7530_reg_write(priv, GSW_PMCR(5), FORCE_MODE); in mt7620_gsw_config_mt7530()
735 mt7530_reg_write(priv, GSW_PMCR(6), FORCE_MODE); in mt7620_gsw_config_mt7530()
738 mt7530_reg_write(priv, MT7530_SYS_CTRL, SW_SYS_RST | SW_REG_RST); in mt7620_gsw_config_mt7530()
742 mt7530_reg_write(priv, GSW_PMCR(6), in mt7620_gsw_config_mt7530()
750 mt7530_reg_read(priv, MT7530_MHWTRAP, &val); in mt7620_gsw_config_mt7530()
752 mt7530_reg_write(priv, MT7530_MHWTRAP, val); in mt7620_gsw_config_mt7530()
755 mt7530_gsw_set_port_isolation(priv); in mt7620_gsw_config_mt7530()
759 phy_val = mt7620_mii_read(priv, i, MII_BMCR); in mt7620_gsw_config_mt7530()
761 mt7620_mii_write(priv, i, MII_BMCR, phy_val); in mt7620_gsw_config_mt7530()
765 mt7620_phy_restart_an(priv, i); in mt7620_gsw_config_mt7530()
768 static void mt7620_gsw_init(struct mt7620_eth_priv *priv) in mt7620_gsw_init() argument
771 if (priv->port5_mt7530) in mt7620_gsw_init()
772 dm_gpio_set_value(&priv->gpio_swrst, 0); in mt7620_gsw_init()
775 gsw_write(priv, GSW_MFC, FIELD_PREP(BC_FFP, 0x7f) | in mt7620_gsw_init()
780 mt7620_setup_gmac_mode(priv, 1, priv->port_cfg[1].mode); in mt7620_gsw_init()
781 mt7620_setup_gmac_mode(priv, 2, priv->port_cfg[0].mode); in mt7620_gsw_init()
784 priv->port_cfg[2].force_mode = true; in mt7620_gsw_init()
785 priv->port_cfg[2].duplex = true; in mt7620_gsw_init()
786 priv->port_cfg[2].speed = FORCE_SPEED_1000; in mt7620_gsw_init()
789 mt7620_gsw_setup_port(priv, 4, &priv->port_cfg[0]); in mt7620_gsw_init()
790 mt7620_gsw_setup_port(priv, 5, &priv->port_cfg[1]); in mt7620_gsw_init()
791 mt7620_gsw_setup_port(priv, 6, &priv->port_cfg[2]); in mt7620_gsw_init()
794 mt7620_gsw_set_port_isolation(priv); in mt7620_gsw_init()
797 mt7620_gsw_setup_phy_polling(priv); in mt7620_gsw_init()
800 mt7620_gsw_ephy_init(priv); in mt7620_gsw_init()
803 if (priv->port5_mt7530) in mt7620_gsw_init()
804 mt7620_gsw_config_mt7530(priv); in mt7620_gsw_init()
807 static void mt7620_eth_fifo_init(struct mt7620_eth_priv *priv) in mt7620_eth_fifo_init() argument
809 uintptr_t pkt_base = (uintptr_t)priv->pkt_buf; in mt7620_eth_fifo_init()
812 memset(priv->tx_ring, 0, NUM_TX_DESC * sizeof(struct pdma_tx_desc)); in mt7620_eth_fifo_init()
813 memset(priv->rx_ring, 0, NUM_RX_DESC * sizeof(struct pdma_rx_desc)); in mt7620_eth_fifo_init()
814 memset(priv->pkt_buf, 0, (NUM_TX_DESC + NUM_RX_DESC) * PKTSIZE_ALIGN); in mt7620_eth_fifo_init()
816 priv->tx_ring_noc = (void *)CKSEG1ADDR((uintptr_t)priv->tx_ring); in mt7620_eth_fifo_init()
817 priv->rx_ring_noc = (void *)CKSEG1ADDR((uintptr_t)priv->rx_ring); in mt7620_eth_fifo_init()
818 priv->rx_dma_owner_idx0 = 0; in mt7620_eth_fifo_init()
819 priv->tx_cpu_owner_idx0 = 0; in mt7620_eth_fifo_init()
822 priv->tx_ring_noc[i].txd_info2.LS0 = 1; in mt7620_eth_fifo_init()
823 priv->tx_ring_noc[i].txd_info2.DDONE = 1; in mt7620_eth_fifo_init()
824 priv->tx_ring_noc[i].txd_info4.FP_BMAP = GDMA_DST_PORT_CPU; in mt7620_eth_fifo_init()
825 priv->tx_ring_noc[i].txd_info1.SDP0 = CPHYSADDR(pkt_base); in mt7620_eth_fifo_init()
830 priv->rx_ring_noc[i].rxd_info2.PLEN0 = PKTSIZE_ALIGN; in mt7620_eth_fifo_init()
831 priv->rx_ring_noc[i].rxd_info1.PDP0 = CPHYSADDR(pkt_base); in mt7620_eth_fifo_init()
835 pdma_write(priv, TX_BASE_PTR0, CPHYSADDR(priv->tx_ring_noc)); in mt7620_eth_fifo_init()
836 pdma_write(priv, TX_MAX_CNT0, NUM_TX_DESC); in mt7620_eth_fifo_init()
837 pdma_write(priv, TX_CTX_IDX0, priv->tx_cpu_owner_idx0); in mt7620_eth_fifo_init()
839 pdma_write(priv, RX_BASE_PTR0, CPHYSADDR(priv->rx_ring_noc)); in mt7620_eth_fifo_init()
840 pdma_write(priv, RX_MAX_CNT0, NUM_RX_DESC); in mt7620_eth_fifo_init()
841 pdma_write(priv, RX_CALC_IDX0, NUM_RX_DESC - 1); in mt7620_eth_fifo_init()
843 pdma_write(priv, PDMA_RST_IDX, RST_DTX_IDX0 | RST_DRX_IDX0); in mt7620_eth_fifo_init()
848 struct mt7620_eth_priv *priv = dev_get_priv(dev); in mt7620_eth_start() local
850 mt7620_eth_fifo_init(priv); in mt7620_eth_start()
852 gdma_rmw(priv, GDMA_FWD_CFG, GDMA_DST_PORT, in mt7620_eth_start()
855 pdma_write(priv, PDMA_GLO_CFG, in mt7620_eth_start()
865 struct mt7620_eth_priv *priv = dev_get_priv(dev); in mt7620_eth_stop() local
869 pdma_write(priv, PDMA_GLO_CFG, in mt7620_eth_stop()
873 ret = readl_poll_timeout(priv->fe_base + PDMA_BASE + PDMA_GLO_CFG, in mt7620_eth_stop()
883 struct mt7620_eth_priv *priv = dev_get_priv(dev); in mt7620_eth_write_hwaddr() local
891 gdma_write(priv, GDMA_MAC_ADRH, macaddr_msb); in mt7620_eth_write_hwaddr()
892 gdma_write(priv, GDMA_MAC_ADRL, macaddr_lsb); in mt7620_eth_write_hwaddr()
899 struct mt7620_eth_priv *priv = dev_get_priv(dev); in mt7620_eth_send() local
900 u32 idx = priv->tx_cpu_owner_idx0; in mt7620_eth_send()
903 if (!priv->tx_ring_noc[idx].txd_info2.DDONE) { in mt7620_eth_send()
908 pkt_base = (void *)CKSEG0ADDR(priv->tx_ring_noc[idx].txd_info1.SDP0); in mt7620_eth_send()
912 priv->tx_ring_noc[idx].txd_info2.SDL0 = length; in mt7620_eth_send()
913 priv->tx_ring_noc[idx].txd_info2.DDONE = 0; in mt7620_eth_send()
915 priv->tx_cpu_owner_idx0 = (priv->tx_cpu_owner_idx0 + 1) % NUM_TX_DESC; in mt7620_eth_send()
916 pdma_write(priv, TX_CTX_IDX0, priv->tx_cpu_owner_idx0); in mt7620_eth_send()
923 struct mt7620_eth_priv *priv = dev_get_priv(dev); in mt7620_eth_recv() local
924 u32 idx = priv->rx_dma_owner_idx0, length; in mt7620_eth_recv()
927 if (!priv->rx_ring_noc[idx].rxd_info2.DDONE) { in mt7620_eth_recv()
932 length = priv->rx_ring_noc[idx].rxd_info2.PLEN0; in mt7620_eth_recv()
933 pkt_base = (void *)CKSEG0ADDR(priv->rx_ring_noc[idx].rxd_info1.PDP0); in mt7620_eth_recv()
944 struct mt7620_eth_priv *priv = dev_get_priv(dev); in mt7620_eth_free_pkt() local
945 u32 idx = priv->rx_dma_owner_idx0; in mt7620_eth_free_pkt()
947 priv->rx_ring_noc[idx].rxd_info2.DDONE = 0; in mt7620_eth_free_pkt()
948 priv->rx_ring_noc[idx].rxd_info2.LS0 = 0; in mt7620_eth_free_pkt()
949 priv->rx_ring_noc[idx].rxd_info2.PLEN0 = PKTSIZE_ALIGN; in mt7620_eth_free_pkt()
951 pdma_write(priv, RX_CALC_IDX0, idx); in mt7620_eth_free_pkt()
952 priv->rx_dma_owner_idx0 = (priv->rx_dma_owner_idx0 + 1) % NUM_RX_DESC; in mt7620_eth_free_pkt()
966 static int mt7620_eth_alloc_rings_pkts(struct mt7620_eth_priv *priv) in mt7620_eth_alloc_rings_pkts() argument
968 priv->tx_ring = memalign(ARCH_DMA_MINALIGN, in mt7620_eth_alloc_rings_pkts()
970 if (!priv->tx_ring) { in mt7620_eth_alloc_rings_pkts()
971 dev_err(priv->dev, "mt7620_eth: unable to alloc tx ring\n"); in mt7620_eth_alloc_rings_pkts()
975 priv->rx_ring = memalign(ARCH_DMA_MINALIGN, in mt7620_eth_alloc_rings_pkts()
977 if (!priv->rx_ring) { in mt7620_eth_alloc_rings_pkts()
978 dev_err(priv->dev, "mt7620_eth: unable to alloc rx ring\n"); in mt7620_eth_alloc_rings_pkts()
982 priv->pkt_buf = memalign(ARCH_DMA_MINALIGN, in mt7620_eth_alloc_rings_pkts()
984 if (!priv->pkt_buf) { in mt7620_eth_alloc_rings_pkts()
985 dev_err(priv->dev, "mt7620_eth: unable to alloc pkt buffer\n"); in mt7620_eth_alloc_rings_pkts()
992 if (priv->tx_ring) in mt7620_eth_alloc_rings_pkts()
993 free(priv->tx_ring); in mt7620_eth_alloc_rings_pkts()
995 if (priv->rx_ring) in mt7620_eth_alloc_rings_pkts()
996 free(priv->rx_ring); in mt7620_eth_alloc_rings_pkts()
1001 static void mt7620_eth_free_rings_pkts(struct mt7620_eth_priv *priv) in mt7620_eth_free_rings_pkts() argument
1003 free(priv->tx_ring); in mt7620_eth_free_rings_pkts()
1004 free(priv->rx_ring); in mt7620_eth_free_rings_pkts()
1005 free(priv->pkt_buf); in mt7620_eth_free_rings_pkts()
1010 struct mt7620_eth_priv *priv = dev_get_priv(dev); in mt7620_eth_probe() local
1014 misc_ioctl(priv->sysc, MT7620_SYSC_IOCTL_SET_PCIE_MODE, &pcie_mode); in mt7620_eth_probe()
1016 clk_enable_bulk(&priv->clks); in mt7620_eth_probe()
1018 reset_assert_bulk(&priv->rsts); in mt7620_eth_probe()
1020 reset_deassert_bulk(&priv->rsts); in mt7620_eth_probe()
1023 ret = mt7620_eth_alloc_rings_pkts(priv); in mt7620_eth_probe()
1031 mt7620_gsw_init(priv); in mt7620_eth_probe()
1038 struct mt7620_eth_priv *priv = dev_get_priv(dev); in mt7620_eth_remove() local
1042 mt7620_eth_free_rings_pkts(priv); in mt7620_eth_remove()
1047 static int mt7620_eth_parse_gsw_port(struct mt7620_eth_priv *priv, u32 idx, in mt7620_eth_parse_gsw_port() argument
1059 dev_err(priv->dev, "mt7620_eth: invalid phy-mode\n"); in mt7620_eth_parse_gsw_port()
1070 dev_err(priv->dev, in mt7620_eth_parse_gsw_port()
1075 priv->port_cfg[idx].mode = mode; in mt7620_eth_parse_gsw_port()
1077 priv->port_cfg[idx].mode = PHY_INTERFACE_MODE_NONE; in mt7620_eth_parse_gsw_port()
1082 priv->port_cfg[idx].force_mode = 1; in mt7620_eth_parse_gsw_port()
1083 priv->port_cfg[idx].duplex = ofnode_read_bool(subnode, in mt7620_eth_parse_gsw_port()
1088 priv->port_cfg[idx].speed = FORCE_SPEED_10; in mt7620_eth_parse_gsw_port()
1091 priv->port_cfg[idx].speed = FORCE_SPEED_100; in mt7620_eth_parse_gsw_port()
1094 priv->port_cfg[idx].speed = FORCE_SPEED_1000; in mt7620_eth_parse_gsw_port()
1097 dev_err(priv->dev, in mt7620_eth_parse_gsw_port()
1103 priv->port5_mt7530 = true; in mt7620_eth_parse_gsw_port()
1106 "mediatek,mt7530-reset", 0, &priv->gpio_swrst, in mt7620_eth_parse_gsw_port()
1109 dev_err(priv->dev, in mt7620_eth_parse_gsw_port()
1120 dev_err(priv->dev, "mt7620_eth: invalid phy address\n"); in mt7620_eth_parse_gsw_port()
1124 priv->port_cfg[idx].phy_addr = phy_addr; in mt7620_eth_parse_gsw_port()
1126 priv->port_cfg[idx].phy_addr = -1; in mt7620_eth_parse_gsw_port()
1134 struct mt7620_eth_priv *priv = dev_get_priv(dev); in mt7620_eth_parse_gsw_cfg() local
1140 ret = mt7620_eth_parse_gsw_port(priv, 0, subnode); in mt7620_eth_parse_gsw_cfg()
1144 priv->port_cfg[0].mode = PHY_INTERFACE_MODE_NONE; in mt7620_eth_parse_gsw_cfg()
1149 return mt7620_eth_parse_gsw_port(priv, 1, subnode); in mt7620_eth_parse_gsw_cfg()
1151 priv->port_cfg[1].mode = PHY_INTERFACE_MODE_NONE; in mt7620_eth_parse_gsw_cfg()
1158 struct mt7620_eth_priv *priv = dev_get_priv(dev); in mt7620_eth_of_to_plat() local
1164 priv->dev = dev; in mt7620_eth_of_to_plat()
1174 &priv->sysc); in mt7620_eth_of_to_plat()
1180 priv->fe_base = dev_remap_addr_name(dev, "fe"); in mt7620_eth_of_to_plat()
1181 if (!priv->fe_base) { in mt7620_eth_of_to_plat()
1186 priv->gsw_base = dev_remap_addr_name(dev, "esw"); in mt7620_eth_of_to_plat()
1187 if (!priv->gsw_base) { in mt7620_eth_of_to_plat()
1192 ret = reset_get_bulk(dev, &priv->rsts); in mt7620_eth_of_to_plat()
1198 ret = clk_get_bulk(dev, &priv->clks); in mt7620_eth_of_to_plat()