Lines Matching refs:priv
166 int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg);
167 int (*mii_write)(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 val);
168 int (*mmd_read)(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg);
169 int (*mmd_write)(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg,
183 int (*switch_init)(struct mtk_eth_priv *priv);
194 static void mtk_pdma_write(struct mtk_eth_priv *priv, u32 reg, u32 val) in mtk_pdma_write() argument
196 writel(val, priv->fe_base + PDMA_BASE + reg); in mtk_pdma_write()
199 static void mtk_pdma_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, in mtk_pdma_rmw() argument
202 clrsetbits_le32(priv->fe_base + PDMA_BASE + reg, clr, set); in mtk_pdma_rmw()
205 static void mtk_gdma_write(struct mtk_eth_priv *priv, int no, u32 reg, in mtk_gdma_write() argument
215 writel(val, priv->fe_base + gdma_base + reg); in mtk_gdma_write()
218 static u32 mtk_gmac_read(struct mtk_eth_priv *priv, u32 reg) in mtk_gmac_read() argument
220 return readl(priv->gmac_base + reg); in mtk_gmac_read()
223 static void mtk_gmac_write(struct mtk_eth_priv *priv, u32 reg, u32 val) in mtk_gmac_write() argument
225 writel(val, priv->gmac_base + reg); in mtk_gmac_write()
228 static void mtk_gmac_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set) in mtk_gmac_rmw() argument
230 clrsetbits_le32(priv->gmac_base + reg, clr, set); in mtk_gmac_rmw()
233 static void mtk_ethsys_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, in mtk_ethsys_rmw() argument
236 clrsetbits_le32(priv->ethsys_base + reg, clr, set); in mtk_ethsys_rmw()
240 static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data, in mtk_mii_rw() argument
254 mtk_gmac_write(priv, GMAC_PIAC_REG, val | PHY_ACS_ST); in mtk_mii_rw()
256 ret = wait_for_bit_le32(priv->gmac_base + GMAC_PIAC_REG, in mtk_mii_rw()
264 val = mtk_gmac_read(priv, GMAC_PIAC_REG); in mtk_mii_rw()
272 static int mtk_mii_read(struct mtk_eth_priv *priv, u8 phy, u8 reg) in mtk_mii_read() argument
274 return mtk_mii_rw(priv, phy, reg, 0, MDIO_CMD_READ, MDIO_ST_C22); in mtk_mii_read()
278 static int mtk_mii_write(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data) in mtk_mii_write() argument
280 return mtk_mii_rw(priv, phy, reg, data, MDIO_CMD_WRITE, MDIO_ST_C22); in mtk_mii_write()
284 static int mtk_mmd_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg) in mtk_mmd_read() argument
288 ret = mtk_mii_rw(priv, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45); in mtk_mmd_read()
292 return mtk_mii_rw(priv, addr, devad, 0, MDIO_CMD_READ_C45, in mtk_mmd_read()
297 static int mtk_mmd_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, in mtk_mmd_write() argument
302 ret = mtk_mii_rw(priv, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45); in mtk_mmd_write()
306 return mtk_mii_rw(priv, addr, devad, val, MDIO_CMD_WRITE, in mtk_mmd_write()
311 static int mtk_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, in mtk_mmd_ind_read() argument
316 ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG, in mtk_mmd_ind_read()
322 ret = priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg); in mtk_mmd_ind_read()
326 ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG, in mtk_mmd_ind_read()
332 return priv->mii_read(priv, addr, MII_MMD_ADDR_DATA_REG); in mtk_mmd_ind_read()
336 static int mtk_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, in mtk_mmd_ind_write() argument
341 ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG, in mtk_mmd_ind_write()
347 ret = priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg); in mtk_mmd_ind_write()
351 ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG, in mtk_mmd_ind_write()
357 return priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, val); in mtk_mmd_ind_write()
369 static int mt753x_reg_read(struct mtk_eth_priv *priv, u32 reg, u32 *data) in mt753x_reg_read() argument
374 ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6); in mt753x_reg_read()
379 low_word = mtk_mii_read(priv, priv->mt753x_smi_addr, (reg >> 2) & 0xf); in mt753x_reg_read()
384 high_word = mtk_mii_read(priv, priv->mt753x_smi_addr, 0x10); in mt753x_reg_read()
394 static int mt753x_reg_write(struct mtk_eth_priv *priv, u32 reg, u32 data) in mt753x_reg_write() argument
399 ret = mtk_mii_write(priv, priv->mt753x_smi_addr, 0x1f, reg >> 6); in mt753x_reg_write()
404 ret = mtk_mii_write(priv, priv->mt753x_smi_addr, (reg >> 2) & 0xf, in mt753x_reg_write()
410 return mtk_mii_write(priv, priv->mt753x_smi_addr, 0x10, data >> 16); in mt753x_reg_write()
413 static void mt753x_reg_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, in mt753x_reg_rmw() argument
418 mt753x_reg_read(priv, reg, &val); in mt753x_reg_rmw()
421 mt753x_reg_write(priv, reg, val); in mt753x_reg_rmw()
425 static int mt7531_mii_rw(struct mtk_eth_priv *priv, int phy, int reg, u16 data, in mt7531_mii_rw() argument
440 mt753x_reg_write(priv, MT7531_PHY_IAC, val | PHY_ACS_ST); in mt7531_mii_rw()
445 mt753x_reg_read(priv, MT7531_PHY_IAC, &val); in mt7531_mii_rw()
455 mt753x_reg_read(priv, MT7531_PHY_IAC, &val); in mt7531_mii_rw()
462 static int mt7531_mii_ind_read(struct mtk_eth_priv *priv, u8 phy, u8 reg) in mt7531_mii_ind_read() argument
469 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, phy); in mt7531_mii_ind_read()
471 return mt7531_mii_rw(priv, phy_addr, reg, 0, MDIO_CMD_READ, in mt7531_mii_ind_read()
475 static int mt7531_mii_ind_write(struct mtk_eth_priv *priv, u8 phy, u8 reg, in mt7531_mii_ind_write() argument
483 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, phy); in mt7531_mii_ind_write()
485 return mt7531_mii_rw(priv, phy_addr, reg, val, MDIO_CMD_WRITE, in mt7531_mii_ind_write()
489 int mt7531_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg) in mt7531_mmd_ind_read() argument
497 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, addr); in mt7531_mmd_ind_read()
499 ret = mt7531_mii_rw(priv, phy_addr, devad, reg, MDIO_CMD_ADDR, in mt7531_mmd_ind_read()
504 return mt7531_mii_rw(priv, phy_addr, devad, 0, MDIO_CMD_READ_C45, in mt7531_mmd_ind_read()
508 static int mt7531_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, in mt7531_mmd_ind_write() argument
517 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, addr); in mt7531_mmd_ind_write()
519 ret = mt7531_mii_rw(priv, phy_addr, devad, reg, MDIO_CMD_ADDR, in mt7531_mmd_ind_write()
524 return mt7531_mii_rw(priv, phy_addr, devad, val, MDIO_CMD_WRITE, in mt7531_mmd_ind_write()
530 struct mtk_eth_priv *priv = bus->priv; in mtk_mdio_read() local
533 return priv->mii_read(priv, addr, reg); in mtk_mdio_read()
535 return priv->mmd_read(priv, addr, devad, reg); in mtk_mdio_read()
541 struct mtk_eth_priv *priv = bus->priv; in mtk_mdio_write() local
544 return priv->mii_write(priv, addr, reg, val); in mtk_mdio_write()
546 return priv->mmd_write(priv, addr, devad, reg, val); in mtk_mdio_write()
551 struct mtk_eth_priv *priv = dev_get_priv(dev); in mtk_mdio_register() local
559 switch (priv->sw) { in mtk_mdio_register()
561 priv->mii_read = mtk_mii_read; in mtk_mdio_register()
562 priv->mii_write = mtk_mii_write; in mtk_mdio_register()
563 priv->mmd_read = mtk_mmd_ind_read; in mtk_mdio_register()
564 priv->mmd_write = mtk_mmd_ind_write; in mtk_mdio_register()
567 priv->mii_read = mt7531_mii_ind_read; in mtk_mdio_register()
568 priv->mii_write = mt7531_mii_ind_write; in mtk_mdio_register()
569 priv->mmd_read = mt7531_mmd_ind_read; in mtk_mdio_register()
570 priv->mmd_write = mt7531_mmd_ind_write; in mtk_mdio_register()
573 priv->mii_read = mtk_mii_read; in mtk_mdio_register()
574 priv->mii_write = mtk_mii_write; in mtk_mdio_register()
575 priv->mmd_read = mtk_mmd_read; in mtk_mdio_register()
576 priv->mmd_write = mtk_mmd_write; in mtk_mdio_register()
583 mdio_bus->priv = (void *)priv; in mtk_mdio_register()
590 priv->mdio_bus = mdio_bus; in mtk_mdio_register()
595 static int mt753x_core_reg_read(struct mtk_eth_priv *priv, u32 reg) in mt753x_core_reg_read() argument
597 u8 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, 0); in mt753x_core_reg_read()
599 return priv->mmd_read(priv, phy_addr, 0x1f, reg); in mt753x_core_reg_read()
602 static void mt753x_core_reg_write(struct mtk_eth_priv *priv, u32 reg, u32 val) in mt753x_core_reg_write() argument
604 u8 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, 0); in mt753x_core_reg_write()
606 priv->mmd_write(priv, phy_addr, 0x1f, reg, val); in mt753x_core_reg_write()
609 static int mt7530_pad_clk_setup(struct mtk_eth_priv *priv, int mode) in mt7530_pad_clk_setup() argument
624 mt753x_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, 0); in mt7530_pad_clk_setup()
627 mt753x_core_reg_write(priv, CORE_GSWPLL_GRP1, in mt7530_pad_clk_setup()
632 mt753x_core_reg_write(priv, CORE_GSWPLL_GRP2, in mt7530_pad_clk_setup()
637 mt753x_core_reg_write(priv, CORE_GSWPLL_GRP1, in mt7530_pad_clk_setup()
644 mt753x_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); in mt7530_pad_clk_setup()
647 mt753x_core_reg_write(priv, CORE_PLL_GROUP5, ncpo1); in mt7530_pad_clk_setup()
648 mt753x_core_reg_write(priv, CORE_PLL_GROUP6, 0); in mt7530_pad_clk_setup()
649 mt753x_core_reg_write(priv, CORE_PLL_GROUP10, ssc_delta); in mt7530_pad_clk_setup()
650 mt753x_core_reg_write(priv, CORE_PLL_GROUP11, ssc_delta); in mt7530_pad_clk_setup()
651 mt753x_core_reg_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN | in mt7530_pad_clk_setup()
654 mt753x_core_reg_write(priv, CORE_PLL_GROUP2, in mt7530_pad_clk_setup()
658 mt753x_core_reg_write(priv, CORE_PLL_GROUP7, in mt7530_pad_clk_setup()
663 mt753x_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, in mt7530_pad_clk_setup()
669 static int mt7530_setup(struct mtk_eth_priv *priv) in mt7530_setup() argument
676 mtk_ethsys_rmw(priv, ETHSYS_CLKCFG0_REG, in mt7530_setup()
680 mt753x_reg_read(priv, HWTRAP_REG, &val); in mt7530_setup()
683 mt753x_reg_write(priv, MHWTRAP_REG, val); in mt7530_setup()
687 priv->mt753x_phy_base = (val | 0x7) + 1; in mt7530_setup()
691 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i); in mt7530_setup()
692 phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); in mt7530_setup()
694 priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); in mt7530_setup()
698 mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE); in mt7530_setup()
699 mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE); in mt7530_setup()
702 mt753x_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST); in mt7530_setup()
713 mt753x_reg_write(priv, PMCR_REG(6), val); in mt7530_setup()
716 mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE); in mt7530_setup()
719 mt753x_reg_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_M, P6_INTF_MODE_RGMII); in mt7530_setup()
722 mt753x_reg_read(priv, HWTRAP_REG, &val); in mt7530_setup()
727 mt753x_reg_write(priv, MHWTRAP_REG, val); in mt7530_setup()
730 mt7530_pad_clk_setup(priv, priv->phy_interface); in mt7530_setup()
734 mt753x_reg_write(priv, MT7530_TRGMII_TD_ODT(i), in mt7530_setup()
738 mt753x_reg_rmw(priv, MT7530_TRGMII_RD(i), RD_TAP_M, 16); in mt7530_setup()
742 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i); in mt7530_setup()
743 phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); in mt7530_setup()
745 priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); in mt7530_setup()
751 static void mt7531_core_pll_setup(struct mtk_eth_priv *priv, int mcm) in mt7531_core_pll_setup() argument
754 mt753x_reg_rmw(priv, MT7531_PLLGP_EN, EN_COREPLL, 0); in mt7531_core_pll_setup()
757 mt753x_reg_rmw(priv, MT7531_PLLGP_EN, SW_CLKSW, SW_CLKSW); in mt7531_core_pll_setup()
759 mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_EN, 0); in mt7531_core_pll_setup()
762 mt753x_reg_rmw(priv, MT7531_PLLGP_EN, SW_PLLGP, SW_PLLGP); in mt7531_core_pll_setup()
765 mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_POSDIV_M, in mt7531_core_pll_setup()
770 mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_M, in mt7531_core_pll_setup()
774 mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_CHG, in mt7531_core_pll_setup()
781 mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_SDM_PCW_CHG, 0); in mt7531_core_pll_setup()
784 mt753x_reg_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); in mt7531_core_pll_setup()
787 mt753x_reg_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); in mt7531_core_pll_setup()
790 mt753x_reg_rmw(priv, MT7531_PLLGP_CR0, RG_COREPLL_EN, RG_COREPLL_EN); in mt7531_core_pll_setup()
792 mt753x_reg_rmw(priv, MT7531_PLLGP_EN, EN_COREPLL, EN_COREPLL); in mt7531_core_pll_setup()
797 static int mt7531_port_sgmii_init(struct mtk_eth_priv *priv, in mt7531_port_sgmii_init() argument
806 mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), in mt7531_port_sgmii_init()
810 mt753x_reg_rmw(priv, MT7531_PCS_CONTROL_1(port), in mt7531_port_sgmii_init()
814 mt753x_reg_write(priv, MT7531_SGMII_MODE(port), SGMII_FORCE_MODE); in mt7531_port_sgmii_init()
817 mt753x_reg_rmw(priv, MT7531_QPHY_PWR_STATE_CTRL(port), in mt7531_port_sgmii_init()
823 static int mt7531_port_rgmii_init(struct mtk_eth_priv *priv, u32 port) in mt7531_port_rgmii_init() argument
833 mt753x_reg_read(priv, MT7531_CLKGEN_CTRL, &val); in mt7531_port_rgmii_init()
843 mt753x_reg_write(priv, MT7531_CLKGEN_CTRL, val); in mt7531_port_rgmii_init()
848 static void mt7531_phy_setting(struct mtk_eth_priv *priv) in mt7531_phy_setting() argument
855 priv->mii_write(priv, i, 0x1f, 0x1); in mt7531_phy_setting()
856 val = priv->mii_read(priv, i, PHY_EXT_REG_14); in mt7531_phy_setting()
858 priv->mii_write(priv, i, PHY_EXT_REG_14, val); in mt7531_phy_setting()
861 val = priv->mii_read(priv, i, PHY_EXT_REG_17); in mt7531_phy_setting()
863 priv->mii_write(priv, i, PHY_EXT_REG_17, val); in mt7531_phy_setting()
865 val = priv->mmd_read(priv, i, 0x1e, PHY_DEV1E_REG_0C6); in mt7531_phy_setting()
868 priv->mmd_write(priv, i, 0x1e, PHY_DEV1E_REG_0C6, val); in mt7531_phy_setting()
872 static int mt7531_setup(struct mtk_eth_priv *priv) in mt7531_setup() argument
880 priv->mt753x_phy_base = (priv->mt753x_smi_addr + 1) & in mt7531_setup()
885 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i); in mt7531_setup()
886 phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); in mt7531_setup()
888 priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); in mt7531_setup()
892 mt753x_reg_write(priv, PMCR_REG(5), FORCE_MODE_LNK); in mt7531_setup()
893 mt753x_reg_write(priv, PMCR_REG(6), FORCE_MODE_LNK); in mt7531_setup()
896 mt753x_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST); in mt7531_setup()
900 mt753x_reg_rmw(priv, MT7531_SMT0_IOLB, SMT_IOLB_5_SMI_MDC_EN, in mt7531_setup()
903 mt7531_core_pll_setup(priv, priv->mcm); in mt7531_setup()
905 mt753x_reg_read(priv, MT7531_TOP_SIG_SR, &val); in mt7531_setup()
909 switch (priv->phy_interface) { in mt7531_setup()
912 mt7531_port_rgmii_init(priv, 5); in mt7531_setup()
915 mt7531_port_sgmii_init(priv, 6); in mt7531_setup()
917 mt7531_port_sgmii_init(priv, 5); in mt7531_setup()
931 mt753x_reg_write(priv, PMCR_REG(5), pmcr); in mt7531_setup()
932 mt753x_reg_write(priv, PMCR_REG(6), pmcr); in mt7531_setup()
936 phy_addr = MT753X_PHY_ADDR(priv->mt753x_phy_base, i); in mt7531_setup()
937 phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); in mt7531_setup()
939 priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); in mt7531_setup()
942 mt7531_phy_setting(priv); in mt7531_setup()
945 val = mt753x_core_reg_read(priv, CORE_PLL_GROUP4); in mt7531_setup()
948 mt753x_core_reg_write(priv, CORE_PLL_GROUP4, val); in mt7531_setup()
953 int mt753x_switch_init(struct mtk_eth_priv *priv) in mt753x_switch_init() argument
959 if (priv->mcm) { in mt753x_switch_init()
960 reset_assert(&priv->rst_mcm); in mt753x_switch_init()
962 reset_deassert(&priv->rst_mcm); in mt753x_switch_init()
964 } else if (dm_gpio_is_valid(&priv->rst_gpio)) { in mt753x_switch_init()
965 dm_gpio_set_value(&priv->rst_gpio, 0); in mt753x_switch_init()
967 dm_gpio_set_value(&priv->rst_gpio, 1); in mt753x_switch_init()
971 ret = priv->switch_init(priv); in mt753x_switch_init()
979 mt753x_reg_write(priv, PCR_REG(i), in mt753x_switch_init()
982 mt753x_reg_write(priv, PCR_REG(i), in mt753x_switch_init()
986 mt753x_reg_write(priv, PVC_REG(i), in mt753x_switch_init()
994 static void mtk_phy_link_adjust(struct mtk_eth_priv *priv) in mtk_phy_link_adjust() argument
1006 switch (priv->phydev->speed) { in mtk_phy_link_adjust()
1018 if (priv->phydev->link) in mtk_phy_link_adjust()
1021 if (priv->phydev->duplex) { in mtk_phy_link_adjust()
1024 if (priv->phydev->pause) in mtk_phy_link_adjust()
1026 if (priv->phydev->asym_pause) in mtk_phy_link_adjust()
1029 if (priv->phydev->advertising & ADVERTISED_Pause) in mtk_phy_link_adjust()
1031 if (priv->phydev->advertising & ADVERTISED_Asym_Pause) in mtk_phy_link_adjust()
1046 mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), mcr); in mtk_phy_link_adjust()
1049 static int mtk_phy_start(struct mtk_eth_priv *priv) in mtk_phy_start() argument
1051 struct phy_device *phydev = priv->phydev; in mtk_phy_start()
1066 mtk_phy_link_adjust(priv); in mtk_phy_start()
1077 struct mtk_eth_priv *priv = dev_get_priv(dev); in mtk_phy_probe() local
1080 phydev = phy_connect(priv->mdio_bus, priv->phy_addr, dev, in mtk_phy_probe()
1081 priv->phy_interface); in mtk_phy_probe()
1088 priv->phydev = phydev; in mtk_phy_probe()
1094 static void mtk_sgmii_init(struct mtk_eth_priv *priv) in mtk_sgmii_init() argument
1097 clrsetbits_le32(priv->sgmii_base + ((priv->soc == SOC_MT7622) ? in mtk_sgmii_init()
1102 clrsetbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1, in mtk_sgmii_init()
1106 writel(SGMII_FORCE_MODE, priv->sgmii_base + SGMSYS_SGMII_MODE); in mtk_sgmii_init()
1109 clrsetbits_le32(priv->sgmii_base + SGMSYS_QPHY_PWR_STATE_CTRL, in mtk_sgmii_init()
1113 static void mtk_mac_init(struct mtk_eth_priv *priv) in mtk_mac_init() argument
1118 switch (priv->phy_interface) { in mtk_mac_init()
1125 mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, SYSCFG0_SGMII_SEL_M, in mtk_mac_init()
1126 SYSCFG0_SGMII_SEL(priv->gmac_id)); in mtk_mac_init()
1127 mtk_sgmii_init(priv); in mtk_mac_init()
1141 mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, in mtk_mac_init()
1142 SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id), in mtk_mac_init()
1143 ge_mode << SYSCFG0_GE_MODE_S(priv->gmac_id)); in mtk_mac_init()
1145 if (priv->force_mode) { in mtk_mac_init()
1153 switch (priv->speed) { in mtk_mac_init()
1165 if (priv->duplex) in mtk_mac_init()
1168 mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), mcr); in mtk_mac_init()
1171 if (priv->soc == SOC_MT7623) { in mtk_mac_init()
1174 mtk_gmac_write(priv, GMAC_TRGMII_TD_ODT(i), in mtk_mac_init()
1178 mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, 0, in mtk_mac_init()
1180 mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, RX_RST, 0); in mtk_mac_init()
1184 static void mtk_eth_fifo_init(struct mtk_eth_priv *priv) in mtk_eth_fifo_init() argument
1186 char *pkt_base = priv->pkt_pool; in mtk_eth_fifo_init()
1189 mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, 0xffff0000, 0); in mtk_eth_fifo_init()
1192 memset(priv->tx_ring_noc, 0, NUM_TX_DESC * sizeof(struct pdma_txdesc)); in mtk_eth_fifo_init()
1193 memset(priv->rx_ring_noc, 0, NUM_RX_DESC * sizeof(struct pdma_rxdesc)); in mtk_eth_fifo_init()
1194 memset(priv->pkt_pool, 0, TOTAL_PKT_BUF_SIZE); in mtk_eth_fifo_init()
1199 priv->rx_dma_owner_idx0 = 0; in mtk_eth_fifo_init()
1200 priv->tx_cpu_owner_idx0 = 0; in mtk_eth_fifo_init()
1203 priv->tx_ring_noc[i].txd_info2.LS0 = 1; in mtk_eth_fifo_init()
1204 priv->tx_ring_noc[i].txd_info2.DDONE = 1; in mtk_eth_fifo_init()
1205 priv->tx_ring_noc[i].txd_info4.FPORT = priv->gmac_id + 1; in mtk_eth_fifo_init()
1207 priv->tx_ring_noc[i].txd_info1.SDP0 = virt_to_phys(pkt_base); in mtk_eth_fifo_init()
1212 priv->rx_ring_noc[i].rxd_info2.PLEN0 = PKTSIZE_ALIGN; in mtk_eth_fifo_init()
1213 priv->rx_ring_noc[i].rxd_info1.PDP0 = virt_to_phys(pkt_base); in mtk_eth_fifo_init()
1217 mtk_pdma_write(priv, TX_BASE_PTR_REG(0), in mtk_eth_fifo_init()
1218 virt_to_phys(priv->tx_ring_noc)); in mtk_eth_fifo_init()
1219 mtk_pdma_write(priv, TX_MAX_CNT_REG(0), NUM_TX_DESC); in mtk_eth_fifo_init()
1220 mtk_pdma_write(priv, TX_CTX_IDX_REG(0), priv->tx_cpu_owner_idx0); in mtk_eth_fifo_init()
1222 mtk_pdma_write(priv, RX_BASE_PTR_REG(0), in mtk_eth_fifo_init()
1223 virt_to_phys(priv->rx_ring_noc)); in mtk_eth_fifo_init()
1224 mtk_pdma_write(priv, RX_MAX_CNT_REG(0), NUM_RX_DESC); in mtk_eth_fifo_init()
1225 mtk_pdma_write(priv, RX_CRX_IDX_REG(0), NUM_RX_DESC - 1); in mtk_eth_fifo_init()
1227 mtk_pdma_write(priv, PDMA_RST_IDX_REG, RST_DTX_IDX0 | RST_DRX_IDX0); in mtk_eth_fifo_init()
1232 struct mtk_eth_priv *priv = dev_get_priv(dev); in mtk_eth_start() local
1236 reset_assert(&priv->rst_fe); in mtk_eth_start()
1238 reset_deassert(&priv->rst_fe); in mtk_eth_start()
1242 mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, GDMA_FWD_TO_CPU); in mtk_eth_start()
1244 if (priv->gmac_id == 0) in mtk_eth_start()
1245 mtk_gdma_write(priv, 1, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD); in mtk_eth_start()
1247 mtk_gdma_write(priv, 0, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD); in mtk_eth_start()
1251 mtk_eth_fifo_init(priv); in mtk_eth_start()
1254 if (priv->sw == SW_NONE) { in mtk_eth_start()
1255 ret = mtk_phy_start(priv); in mtk_eth_start()
1260 mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, 0, in mtk_eth_start()
1269 struct mtk_eth_priv *priv = dev_get_priv(dev); in mtk_eth_stop() local
1271 mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, in mtk_eth_stop()
1275 wait_for_bit_le32(priv->fe_base + PDMA_BASE + PDMA_GLO_CFG_REG, in mtk_eth_stop()
1282 struct mtk_eth_priv *priv = dev_get_priv(dev); in mtk_eth_write_hwaddr() local
1290 mtk_gdma_write(priv, priv->gmac_id, GDMA_MAC_MSB_REG, macaddr_msb); in mtk_eth_write_hwaddr()
1291 mtk_gdma_write(priv, priv->gmac_id, GDMA_MAC_LSB_REG, macaddr_lsb); in mtk_eth_write_hwaddr()
1298 struct mtk_eth_priv *priv = dev_get_priv(dev); in mtk_eth_send() local
1299 u32 idx = priv->tx_cpu_owner_idx0; in mtk_eth_send()
1302 if (!priv->tx_ring_noc[idx].txd_info2.DDONE) { in mtk_eth_send()
1307 pkt_base = (void *)phys_to_virt(priv->tx_ring_noc[idx].txd_info1.SDP0); in mtk_eth_send()
1312 priv->tx_ring_noc[idx].txd_info2.SDL0 = length; in mtk_eth_send()
1313 priv->tx_ring_noc[idx].txd_info2.DDONE = 0; in mtk_eth_send()
1315 priv->tx_cpu_owner_idx0 = (priv->tx_cpu_owner_idx0 + 1) % NUM_TX_DESC; in mtk_eth_send()
1316 mtk_pdma_write(priv, TX_CTX_IDX_REG(0), priv->tx_cpu_owner_idx0); in mtk_eth_send()
1323 struct mtk_eth_priv *priv = dev_get_priv(dev); in mtk_eth_recv() local
1324 u32 idx = priv->rx_dma_owner_idx0; in mtk_eth_recv()
1328 if (!priv->rx_ring_noc[idx].rxd_info2.DDONE) { in mtk_eth_recv()
1333 length = priv->rx_ring_noc[idx].rxd_info2.PLEN0; in mtk_eth_recv()
1334 pkt_base = (void *)phys_to_virt(priv->rx_ring_noc[idx].rxd_info1.PDP0); in mtk_eth_recv()
1346 struct mtk_eth_priv *priv = dev_get_priv(dev); in mtk_eth_free_pkt() local
1347 u32 idx = priv->rx_dma_owner_idx0; in mtk_eth_free_pkt()
1349 priv->rx_ring_noc[idx].rxd_info2.DDONE = 0; in mtk_eth_free_pkt()
1350 priv->rx_ring_noc[idx].rxd_info2.LS0 = 0; in mtk_eth_free_pkt()
1351 priv->rx_ring_noc[idx].rxd_info2.PLEN0 = PKTSIZE_ALIGN; in mtk_eth_free_pkt()
1353 mtk_pdma_write(priv, RX_CRX_IDX_REG(0), idx); in mtk_eth_free_pkt()
1354 priv->rx_dma_owner_idx0 = (priv->rx_dma_owner_idx0 + 1) % NUM_RX_DESC; in mtk_eth_free_pkt()
1362 struct mtk_eth_priv *priv = dev_get_priv(dev); in mtk_eth_probe() local
1367 priv->fe_base = (void *)iobase; in mtk_eth_probe()
1370 priv->gmac_base = (void *)(iobase + GMAC_BASE); in mtk_eth_probe()
1378 priv->tx_ring_noc = (struct pdma_txdesc *) in mtk_eth_probe()
1381 priv->rx_ring_noc = (struct pdma_rxdesc *) in mtk_eth_probe()
1386 mtk_mac_init(priv); in mtk_eth_probe()
1389 if (priv->sw == SW_NONE) in mtk_eth_probe()
1393 return mt753x_switch_init(priv); in mtk_eth_probe()
1398 struct mtk_eth_priv *priv = dev_get_priv(dev); in mtk_eth_remove() local
1401 mdio_unregister(priv->mdio_bus); in mtk_eth_remove()
1402 mdio_free(priv->mdio_bus); in mtk_eth_remove()
1413 struct mtk_eth_priv *priv = dev_get_priv(dev); in mtk_eth_of_to_plat() local
1420 priv->soc = dev_get_driver_data(dev); in mtk_eth_of_to_plat()
1434 priv->ethsys_base = regmap_get_range(regmap, 0); in mtk_eth_of_to_plat()
1435 if (!priv->ethsys_base) { in mtk_eth_of_to_plat()
1441 ret = reset_get_by_name(dev, "fe", &priv->rst_fe); in mtk_eth_of_to_plat()
1447 priv->gmac_id = dev_read_u32_default(dev, "mediatek,gmac-id", 0); in mtk_eth_of_to_plat()
1453 priv->phy_interface = pdata->phy_interface; in mtk_eth_of_to_plat()
1462 priv->force_mode = 1; in mtk_eth_of_to_plat()
1463 priv->speed = ofnode_read_u32_default(subnode, "speed", 0); in mtk_eth_of_to_plat()
1464 priv->duplex = ofnode_read_bool(subnode, "full-duplex"); in mtk_eth_of_to_plat()
1466 if (priv->speed != SPEED_10 && priv->speed != SPEED_100 && in mtk_eth_of_to_plat()
1467 priv->speed != SPEED_1000) { in mtk_eth_of_to_plat()
1473 if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII) { in mtk_eth_of_to_plat()
1485 priv->sgmii_base = regmap_get_range(regmap, 0); in mtk_eth_of_to_plat()
1487 if (!priv->sgmii_base) { in mtk_eth_of_to_plat()
1494 priv->sw = SW_NONE; in mtk_eth_of_to_plat()
1495 priv->switch_init = NULL; in mtk_eth_of_to_plat()
1500 priv->sw = SW_MT7530; in mtk_eth_of_to_plat()
1501 priv->switch_init = mt7530_setup; in mtk_eth_of_to_plat()
1502 priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR; in mtk_eth_of_to_plat()
1504 priv->sw = SW_MT7531; in mtk_eth_of_to_plat()
1505 priv->switch_init = mt7531_setup; in mtk_eth_of_to_plat()
1506 priv->mt753x_smi_addr = MT753X_DFL_SMI_ADDR; in mtk_eth_of_to_plat()
1512 priv->mcm = dev_read_bool(dev, "mediatek,mcm"); in mtk_eth_of_to_plat()
1513 if (priv->mcm) { in mtk_eth_of_to_plat()
1514 ret = reset_get_by_name(dev, "mcm", &priv->rst_mcm); in mtk_eth_of_to_plat()
1521 &priv->rst_gpio, GPIOD_IS_OUT); in mtk_eth_of_to_plat()
1531 priv->phy_addr = ofnode_read_s32_default(args.node, "reg", -1); in mtk_eth_of_to_plat()
1532 if (priv->phy_addr < 0) { in mtk_eth_of_to_plat()