Lines Matching refs:phydev
107 static int m88e1xxx_phy_extread(struct phy_device *phydev, int addr, in m88e1xxx_phy_extread() argument
110 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE); in m88e1xxx_phy_extread()
113 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr); in m88e1xxx_phy_extread()
114 val = phy_read(phydev, MDIO_DEVAD_NONE, regnum); in m88e1xxx_phy_extread()
115 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage); in m88e1xxx_phy_extread()
120 static int m88e1xxx_phy_extwrite(struct phy_device *phydev, int addr, in m88e1xxx_phy_extwrite() argument
123 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE); in m88e1xxx_phy_extwrite()
125 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr); in m88e1xxx_phy_extwrite()
126 phy_write(phydev, MDIO_DEVAD_NONE, regnum, val); in m88e1xxx_phy_extwrite()
127 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage); in m88e1xxx_phy_extwrite()
133 static int m88e1011s_config(struct phy_device *phydev) in m88e1011s_config() argument
136 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in m88e1011s_config()
138 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); in m88e1011s_config()
139 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c); in m88e1011s_config()
140 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); in m88e1011s_config()
141 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0); in m88e1011s_config()
142 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); in m88e1011s_config()
144 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in m88e1011s_config()
146 genphy_config_aneg(phydev); in m88e1011s_config()
154 static int m88e1xxx_parse_status(struct phy_device *phydev) in m88e1xxx_parse_status() argument
159 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_STATUS); in m88e1xxx_parse_status()
170 phydev->link = 0; in m88e1xxx_parse_status()
177 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, in m88e1xxx_parse_status()
184 phydev->link = 1; in m88e1xxx_parse_status()
186 phydev->link = 0; in m88e1xxx_parse_status()
190 phydev->duplex = DUPLEX_FULL; in m88e1xxx_parse_status()
192 phydev->duplex = DUPLEX_HALF; in m88e1xxx_parse_status()
198 phydev->speed = SPEED_1000; in m88e1xxx_parse_status()
201 phydev->speed = SPEED_100; in m88e1xxx_parse_status()
204 phydev->speed = SPEED_10; in m88e1xxx_parse_status()
211 static int m88e1011s_startup(struct phy_device *phydev) in m88e1011s_startup() argument
215 ret = genphy_update_link(phydev); in m88e1011s_startup()
219 return m88e1xxx_parse_status(phydev); in m88e1011s_startup()
223 static int m88e1111s_config(struct phy_device *phydev) in m88e1111s_config() argument
227 if (phy_interface_is_rgmii(phydev)) { in m88e1111s_config()
228 reg = phy_read(phydev, in m88e1111s_config()
230 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) || in m88e1111s_config()
231 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) { in m88e1111s_config()
233 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { in m88e1111s_config()
236 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { in m88e1111s_config()
241 phy_write(phydev, in m88e1111s_config()
244 reg = phy_read(phydev, in m88e1111s_config()
254 phy_write(phydev, in m88e1111s_config()
258 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in m88e1111s_config()
259 reg = phy_read(phydev, in m88e1111s_config()
266 phy_write(phydev, MDIO_DEVAD_NONE, in m88e1111s_config()
270 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) { in m88e1111s_config()
271 reg = phy_read(phydev, in m88e1111s_config()
274 phy_write(phydev, in m88e1111s_config()
277 reg = phy_read(phydev, MDIO_DEVAD_NONE, in m88e1111s_config()
282 phy_write(phydev, MDIO_DEVAD_NONE, in m88e1111s_config()
286 phy_reset(phydev); in m88e1111s_config()
288 reg = phy_read(phydev, MDIO_DEVAD_NONE, in m88e1111s_config()
294 phy_write(phydev, MDIO_DEVAD_NONE, in m88e1111s_config()
299 phy_reset(phydev); in m88e1111s_config()
301 genphy_config_aneg(phydev); in m88e1111s_config()
302 genphy_restart_aneg(phydev); in m88e1111s_config()
310 void m88e151x_phy_writebits(struct phy_device *phydev, in m88e151x_phy_writebits() argument
320 reg = phy_read(phydev, MDIO_DEVAD_NONE, reg_num); in m88e151x_phy_writebits()
325 phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg); in m88e151x_phy_writebits()
328 static int m88e151x_config(struct phy_device *phydev) in m88e151x_config() argument
338 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00ff); in m88e151x_config()
339 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B); in m88e151x_config()
340 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144); in m88e151x_config()
341 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28); in m88e151x_config()
342 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2146); in m88e151x_config()
343 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xB233); in m88e151x_config()
344 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D); in m88e151x_config()
345 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C); in m88e151x_config()
346 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159); in m88e151x_config()
347 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); in m88e151x_config()
350 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in m88e151x_config()
352 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 18); in m88e151x_config()
355 m88e151x_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL, in m88e151x_config()
359 m88e151x_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL, in m88e151x_config()
363 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0); in m88e151x_config()
368 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in m88e151x_config()
369 reg = phy_read(phydev, MDIO_DEVAD_NONE, in m88e151x_config()
376 phy_write(phydev, MDIO_DEVAD_NONE, in m88e151x_config()
380 if (phy_interface_is_rgmii(phydev)) { in m88e151x_config()
381 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, 2); in m88e151x_config()
383 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR); in m88e151x_config()
385 if (phydev->interface == PHY_INTERFACE_MODE_RGMII || in m88e151x_config()
386 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) in m88e151x_config()
388 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) in m88e151x_config()
390 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) in m88e151x_config()
392 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR, reg); in m88e151x_config()
394 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, 0); in m88e151x_config()
398 phy_reset(phydev); in m88e151x_config()
400 genphy_config_aneg(phydev); in m88e151x_config()
401 genphy_restart_aneg(phydev); in m88e151x_config()
407 static int m88e1118_config(struct phy_device *phydev) in m88e1118_config() argument
410 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0002); in m88e1118_config()
412 phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x1070); in m88e1118_config()
414 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0003); in m88e1118_config()
416 phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x021e); in m88e1118_config()
418 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); in m88e1118_config()
420 return genphy_config_aneg(phydev); in m88e1118_config()
423 static int m88e1118_startup(struct phy_device *phydev) in m88e1118_startup() argument
428 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); in m88e1118_startup()
430 ret = genphy_update_link(phydev); in m88e1118_startup()
434 return m88e1xxx_parse_status(phydev); in m88e1118_startup()
438 static int m88e1121_config(struct phy_device *phydev) in m88e1121_config() argument
443 genphy_config_aneg(phydev); in m88e1121_config()
446 pg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE); in m88e1121_config()
447 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, in m88e1121_config()
450 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_LED_CTRL, in m88e1121_config()
453 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, pg); in m88e1121_config()
456 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_EN, 0); in m88e1121_config()
457 phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_STATUS); in m88e1121_config()
463 static int m88e1145_config(struct phy_device *phydev) in m88e1145_config() argument
468 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x001b); in m88e1145_config()
469 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0x418f); in m88e1145_config()
470 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x0016); in m88e1145_config()
471 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0xa2da); in m88e1145_config()
473 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_SCR, in m88e1145_config()
476 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR); in m88e1145_config()
477 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) in m88e1145_config()
480 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR, reg); in m88e1145_config()
482 genphy_config_aneg(phydev); in m88e1145_config()
485 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in m88e1145_config()
487 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); in m88e1145_config()
492 static int m88e1145_startup(struct phy_device *phydev) in m88e1145_startup() argument
496 ret = genphy_update_link(phydev); in m88e1145_startup()
500 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_LED_CONTROL, in m88e1145_startup()
502 return m88e1xxx_parse_status(phydev); in m88e1145_startup()
506 static int m88e1149_config(struct phy_device *phydev) in m88e1149_config() argument
508 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x1f); in m88e1149_config()
509 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c); in m88e1149_config()
510 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x5); in m88e1149_config()
511 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x0); in m88e1149_config()
512 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); in m88e1149_config()
514 genphy_config_aneg(phydev); in m88e1149_config()
516 phy_reset(phydev); in m88e1149_config()
522 static int m88e1310_config(struct phy_device *phydev) in m88e1310_config() argument
527 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003); in m88e1310_config()
528 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL); in m88e1310_config()
530 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL, reg); in m88e1310_config()
533 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003); in m88e1310_config()
534 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN); in m88e1310_config()
536 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN, reg); in m88e1310_config()
539 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0002); in m88e1310_config()
540 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL); in m88e1310_config()
542 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL, reg); in m88e1310_config()
545 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0000); in m88e1310_config()
547 return genphy_config_aneg(phydev); in m88e1310_config()
550 static int m88e1680_config(struct phy_device *phydev) in m88e1680_config() argument
560 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0004); in m88e1680_config()
561 reg = phy_read(phydev, MDIO_DEVAD_NONE, 27); in m88e1680_config()
563 phy_write(phydev, MDIO_DEVAD_NONE, 27, reg); in m88e1680_config()
566 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00fd); in m88e1680_config()
567 phy_write(phydev, MDIO_DEVAD_NONE, 8, 0x0b53); in m88e1680_config()
568 phy_write(phydev, MDIO_DEVAD_NONE, 7, 0x200d); in m88e1680_config()
569 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); in m88e1680_config()
572 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00ff); in m88e1680_config()
573 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xb030); in m88e1680_config()
574 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x215c); in m88e1680_config()
575 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00fc); in m88e1680_config()
576 phy_write(phydev, MDIO_DEVAD_NONE, 24, 0x888c); in m88e1680_config()
577 phy_write(phydev, MDIO_DEVAD_NONE, 25, 0x888c); in m88e1680_config()
578 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); in m88e1680_config()
579 phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140); in m88e1680_config()
581 res = genphy_config_aneg(phydev); in m88e1680_config()
586 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in m88e1680_config()
588 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); in m88e1680_config()