Lines Matching refs:bus
284 static void vsc8584_csr_write(struct mii_dev *bus, int phy0, u16 addr, u32 val) in vsc8584_csr_write() argument
286 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18, in vsc8584_csr_write()
288 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17, in vsc8584_csr_write()
290 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in vsc8584_csr_write()
294 static int vsc8584_cmd(struct mii_dev *bus, int phy, u16 val) in vsc8584_cmd() argument
299 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8584_cmd()
302 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_PHY_PROC_CMD, in vsc8584_cmd()
307 reg_val = bus->read(bus, phy, MDIO_DEVAD_NONE, in vsc8584_cmd()
313 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8584_cmd()
324 static int vsc8584_micro_deassert_reset(struct mii_dev *bus, int phy, in vsc8584_micro_deassert_reset() argument
329 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8584_micro_deassert_reset()
341 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL, in vsc8584_micro_deassert_reset()
349 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, enable); in vsc8584_micro_deassert_reset()
351 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, release); in vsc8584_micro_deassert_reset()
353 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8584_micro_deassert_reset()
359 static int vsc8584_micro_assert_reset(struct mii_dev *bus, int phy) in vsc8584_micro_assert_reset() argument
364 ret = vsc8584_cmd(bus, phy, PROC_CMD_NOP); in vsc8584_micro_assert_reset()
368 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8584_micro_assert_reset()
371 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL); in vsc8584_micro_assert_reset()
373 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL, reg); in vsc8584_micro_assert_reset()
375 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_TRAP_ROM_ADDR(4), 0x005b); in vsc8584_micro_assert_reset()
376 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_PATCH_RAM_ADDR(4), 0x005b); in vsc8584_micro_assert_reset()
378 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL); in vsc8584_micro_assert_reset()
380 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL, reg); in vsc8584_micro_assert_reset()
382 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_PHY_PROC_CMD, PROC_CMD_NOP); in vsc8584_micro_assert_reset()
384 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8584_micro_assert_reset()
386 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, reg); in vsc8584_micro_assert_reset()
388 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_PHY_PROC_CMD, in vsc8584_micro_assert_reset()
392 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL); in vsc8584_micro_assert_reset()
394 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL, reg); in vsc8584_micro_assert_reset()
396 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8584_micro_assert_reset()
554 static int vsc8584_get_fw_crc(struct mii_dev *bus, int phy, u16 start, in vsc8584_get_fw_crc() argument
559 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8584_get_fw_crc()
562 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_PHY_VERIPHY_CNTL_2, start); in vsc8584_get_fw_crc()
564 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_PHY_VERIPHY_CNTL_3, in vsc8584_get_fw_crc()
567 ret = vsc8584_cmd(bus, phy, PROC_CMD_CRC16); in vsc8584_get_fw_crc()
571 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8584_get_fw_crc()
574 *crc = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_PHY_VERIPHY_CNTL_2); in vsc8584_get_fw_crc()
577 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8584_get_fw_crc()
583 static int vsc8584_patch_fw(struct mii_dev *bus, int phy, const u8 *fw_patch, in vsc8584_patch_fw() argument
588 ret = vsc8584_micro_assert_reset(bus, phy); in vsc8584_patch_fw()
594 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8584_patch_fw()
601 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS, in vsc8584_patch_fw()
604 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL, READ_PRAM | in vsc8584_patch_fw()
606 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_ADDR, 0x0000); in vsc8584_patch_fw()
609 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL, in vsc8584_patch_fw()
613 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL, READ_RAM); in vsc8584_patch_fw()
615 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8584_patch_fw()
621 static bool vsc8574_is_serdes_init(struct mii_dev *bus, int phy) in vsc8574_is_serdes_init() argument
626 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8574_is_serdes_init()
629 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_TRAP_ROM_ADDR(1)); in vsc8574_is_serdes_init()
635 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_PATCH_RAM_ADDR(1)); in vsc8574_is_serdes_init()
641 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL); in vsc8574_is_serdes_init()
647 reg = bus->read(bus, phy, MDIO_DEVAD_NONE, MSCC_DW8051_CNTL_STATUS); in vsc8574_is_serdes_init()
657 bus->write(bus, phy, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8574_is_serdes_init()
665 struct mii_dev *bus = phydev->bus; in vsc8574_config_pre_init() local
681 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8574_config_pre_init()
685 reg = bus->read(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_EXT_CNTL_STATUS); in vsc8574_config_pre_init()
687 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8574_config_pre_init()
695 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_EXT_PHY_CNTL_2, 0x0040); in vsc8574_config_pre_init()
697 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8574_config_pre_init()
700 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_20, 0x4320); in vsc8574_config_pre_init()
701 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_24, 0x0c00); in vsc8574_config_pre_init()
702 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_9, 0x18ca); in vsc8574_config_pre_init()
703 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_5, 0x1b20); in vsc8574_config_pre_init()
705 reg = bus->read(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_8); in vsc8574_config_pre_init()
707 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_8, reg); in vsc8574_config_pre_init()
709 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8574_config_pre_init()
712 vsc8584_csr_write(bus, phy0, 0x0fae, 0x000401bd); in vsc8574_config_pre_init()
713 vsc8584_csr_write(bus, phy0, 0x0fac, 0x000f000f); in vsc8574_config_pre_init()
714 vsc8584_csr_write(bus, phy0, 0x17a0, 0x00a0f147); in vsc8574_config_pre_init()
715 vsc8584_csr_write(bus, phy0, 0x0fe4, 0x00052f54); in vsc8574_config_pre_init()
716 vsc8584_csr_write(bus, phy0, 0x1792, 0x0027303d); in vsc8574_config_pre_init()
717 vsc8584_csr_write(bus, phy0, 0x07fe, 0x00000704); in vsc8574_config_pre_init()
718 vsc8584_csr_write(bus, phy0, 0x0fe0, 0x00060150); in vsc8574_config_pre_init()
719 vsc8584_csr_write(bus, phy0, 0x0f82, 0x0012b00a); in vsc8574_config_pre_init()
720 vsc8584_csr_write(bus, phy0, 0x0f80, 0x00000d74); in vsc8574_config_pre_init()
721 vsc8584_csr_write(bus, phy0, 0x02e0, 0x00000012); in vsc8574_config_pre_init()
722 vsc8584_csr_write(bus, phy0, 0x03a2, 0x00050208); in vsc8574_config_pre_init()
723 vsc8584_csr_write(bus, phy0, 0x03b2, 0x00009186); in vsc8574_config_pre_init()
724 vsc8584_csr_write(bus, phy0, 0x0fb0, 0x000e3700); in vsc8574_config_pre_init()
725 vsc8584_csr_write(bus, phy0, 0x1688, 0x00049f81); in vsc8574_config_pre_init()
726 vsc8584_csr_write(bus, phy0, 0x0fd2, 0x0000ffff); in vsc8574_config_pre_init()
727 vsc8584_csr_write(bus, phy0, 0x168a, 0x00039fa2); in vsc8574_config_pre_init()
728 vsc8584_csr_write(bus, phy0, 0x1690, 0x0020640b); in vsc8574_config_pre_init()
729 vsc8584_csr_write(bus, phy0, 0x0258, 0x00002220); in vsc8574_config_pre_init()
730 vsc8584_csr_write(bus, phy0, 0x025a, 0x00002a20); in vsc8574_config_pre_init()
731 vsc8584_csr_write(bus, phy0, 0x025c, 0x00003060); in vsc8574_config_pre_init()
732 vsc8584_csr_write(bus, phy0, 0x025e, 0x00003fa0); in vsc8574_config_pre_init()
733 vsc8584_csr_write(bus, phy0, 0x03a6, 0x0000e0f0); in vsc8574_config_pre_init()
734 vsc8584_csr_write(bus, phy0, 0x0f92, 0x00001489); in vsc8574_config_pre_init()
735 vsc8584_csr_write(bus, phy0, 0x16a2, 0x00007000); in vsc8574_config_pre_init()
736 vsc8584_csr_write(bus, phy0, 0x16a6, 0x00071448); in vsc8574_config_pre_init()
737 vsc8584_csr_write(bus, phy0, 0x16a0, 0x00eeffdd); in vsc8574_config_pre_init()
738 vsc8584_csr_write(bus, phy0, 0x0fe8, 0x0091b06c); in vsc8574_config_pre_init()
739 vsc8584_csr_write(bus, phy0, 0x0fea, 0x00041600); in vsc8574_config_pre_init()
740 vsc8584_csr_write(bus, phy0, 0x16b0, 0x00eeff00); in vsc8574_config_pre_init()
741 vsc8584_csr_write(bus, phy0, 0x16b2, 0x00007000); in vsc8574_config_pre_init()
742 vsc8584_csr_write(bus, phy0, 0x16b4, 0x00000814); in vsc8574_config_pre_init()
743 vsc8584_csr_write(bus, phy0, 0x0f90, 0x00688980); in vsc8574_config_pre_init()
744 vsc8584_csr_write(bus, phy0, 0x03a4, 0x0000d8f0); in vsc8574_config_pre_init()
745 vsc8584_csr_write(bus, phy0, 0x0fc0, 0x00000400); in vsc8574_config_pre_init()
746 vsc8584_csr_write(bus, phy0, 0x07fa, 0x0050100f); in vsc8574_config_pre_init()
747 vsc8584_csr_write(bus, phy0, 0x0796, 0x00000003); in vsc8574_config_pre_init()
748 vsc8584_csr_write(bus, phy0, 0x07f8, 0x00c3ff98); in vsc8574_config_pre_init()
749 vsc8584_csr_write(bus, phy0, 0x0fa4, 0x0018292a); in vsc8574_config_pre_init()
750 vsc8584_csr_write(bus, phy0, 0x168c, 0x00d2c46f); in vsc8574_config_pre_init()
751 vsc8584_csr_write(bus, phy0, 0x17a2, 0x00000620); in vsc8574_config_pre_init()
752 vsc8584_csr_write(bus, phy0, 0x16a4, 0x0013132f); in vsc8574_config_pre_init()
753 vsc8584_csr_write(bus, phy0, 0x16a8, 0x00000000); in vsc8574_config_pre_init()
754 vsc8584_csr_write(bus, phy0, 0x0ffc, 0x00c0a028); in vsc8574_config_pre_init()
755 vsc8584_csr_write(bus, phy0, 0x0fec, 0x00901c09); in vsc8574_config_pre_init()
756 vsc8584_csr_write(bus, phy0, 0x0fee, 0x0004a6a1); in vsc8574_config_pre_init()
757 vsc8584_csr_write(bus, phy0, 0x0ffe, 0x00b01807); in vsc8574_config_pre_init()
759 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8574_config_pre_init()
762 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e); in vsc8574_config_pre_init()
764 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8574_config_pre_init()
767 vsc8584_csr_write(bus, phy0, 0x0486, 0x0008a518); in vsc8574_config_pre_init()
768 vsc8584_csr_write(bus, phy0, 0x0488, 0x006dc696); in vsc8574_config_pre_init()
769 vsc8584_csr_write(bus, phy0, 0x048a, 0x00000912); in vsc8574_config_pre_init()
770 vsc8584_csr_write(bus, phy0, 0x048e, 0x00000db6); in vsc8574_config_pre_init()
771 vsc8584_csr_write(bus, phy0, 0x049c, 0x00596596); in vsc8574_config_pre_init()
772 vsc8584_csr_write(bus, phy0, 0x049e, 0x00000514); in vsc8574_config_pre_init()
773 vsc8584_csr_write(bus, phy0, 0x04a2, 0x00410280); in vsc8574_config_pre_init()
774 vsc8584_csr_write(bus, phy0, 0x04a4, 0x00000000); in vsc8574_config_pre_init()
775 vsc8584_csr_write(bus, phy0, 0x04a6, 0x00000000); in vsc8574_config_pre_init()
776 vsc8584_csr_write(bus, phy0, 0x04a8, 0x00000000); in vsc8574_config_pre_init()
777 vsc8584_csr_write(bus, phy0, 0x04aa, 0x00000000); in vsc8574_config_pre_init()
778 vsc8584_csr_write(bus, phy0, 0x04ae, 0x007df7dd); in vsc8574_config_pre_init()
779 vsc8584_csr_write(bus, phy0, 0x04b0, 0x006d95d4); in vsc8574_config_pre_init()
780 vsc8584_csr_write(bus, phy0, 0x04b2, 0x00492410); in vsc8574_config_pre_init()
782 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8574_config_pre_init()
785 reg = bus->read(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_8); in vsc8574_config_pre_init()
787 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_8, reg); in vsc8574_config_pre_init()
789 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8574_config_pre_init()
793 reg = bus->read(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_EXT_CNTL_STATUS); in vsc8574_config_pre_init()
795 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8574_config_pre_init()
797 ret = vsc8584_get_fw_crc(bus, phy0, in vsc8574_config_pre_init()
805 serdes_init = vsc8574_is_serdes_init(bus, phy0); in vsc8574_config_pre_init()
808 ret = vsc8584_micro_assert_reset(bus, phy0); in vsc8574_config_pre_init()
819 if (vsc8584_patch_fw(bus, phy0, fw_patch_vsc8574, in vsc8574_config_pre_init()
825 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8574_config_pre_init()
828 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_TRAP_ROM_ADDR(1), in vsc8574_config_pre_init()
830 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PATCH_RAM_ADDR(1), in vsc8574_config_pre_init()
833 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_INT_MEM_CNTL, in vsc8574_config_pre_init()
836 vsc8584_micro_deassert_reset(bus, phy0, false); in vsc8574_config_pre_init()
838 ret = vsc8584_get_fw_crc(bus, phy0, in vsc8574_config_pre_init()
849 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8574_config_pre_init()
852 ret = vsc8584_cmd(bus, phy0, PROC_CMD_1588_DEFAULT_INIT | in vsc8574_config_pre_init()
856 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8574_config_pre_init()
864 struct mii_dev *bus = phydev->bus; in vsc8584_config_pre_init() local
884 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8584_config_pre_init()
888 reg = bus->read(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_EXT_CNTL_STATUS); in vsc8584_config_pre_init()
890 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8584_config_pre_init()
898 reg = bus->read(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_BYPASS_CONTROL); in vsc8584_config_pre_init()
900 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_BYPASS_CONTROL, reg); in vsc8584_config_pre_init()
902 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8584_config_pre_init()
905 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_SERDES_TX_CRC_ERR_CNT, in vsc8584_config_pre_init()
908 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8584_config_pre_init()
911 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_5, 0x1f20); in vsc8584_config_pre_init()
913 reg = bus->read(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_8); in vsc8584_config_pre_init()
915 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_8, reg); in vsc8584_config_pre_init()
917 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8584_config_pre_init()
920 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, 0xafa4); in vsc8584_config_pre_init()
922 reg = bus->read(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18); in vsc8584_config_pre_init()
925 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18, reg); in vsc8584_config_pre_init()
927 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, 0x8fa4); in vsc8584_config_pre_init()
929 vsc8584_csr_write(bus, phy0, 0x07fa, 0x0050100f); in vsc8584_config_pre_init()
930 vsc8584_csr_write(bus, phy0, 0x1688, 0x00049f81); in vsc8584_config_pre_init()
931 vsc8584_csr_write(bus, phy0, 0x0f90, 0x00688980); in vsc8584_config_pre_init()
932 vsc8584_csr_write(bus, phy0, 0x03a4, 0x0000d8f0); in vsc8584_config_pre_init()
933 vsc8584_csr_write(bus, phy0, 0x0fc0, 0x00000400); in vsc8584_config_pre_init()
934 vsc8584_csr_write(bus, phy0, 0x0f82, 0x0012b002); in vsc8584_config_pre_init()
935 vsc8584_csr_write(bus, phy0, 0x1686, 0x00000004); in vsc8584_config_pre_init()
936 vsc8584_csr_write(bus, phy0, 0x168c, 0x00d2c46f); in vsc8584_config_pre_init()
937 vsc8584_csr_write(bus, phy0, 0x17a2, 0x00000620); in vsc8584_config_pre_init()
938 vsc8584_csr_write(bus, phy0, 0x16a0, 0x00eeffdd); in vsc8584_config_pre_init()
939 vsc8584_csr_write(bus, phy0, 0x16a6, 0x00071448); in vsc8584_config_pre_init()
940 vsc8584_csr_write(bus, phy0, 0x16a4, 0x0013132f); in vsc8584_config_pre_init()
941 vsc8584_csr_write(bus, phy0, 0x16a8, 0x00000000); in vsc8584_config_pre_init()
942 vsc8584_csr_write(bus, phy0, 0x0ffc, 0x00c0a028); in vsc8584_config_pre_init()
943 vsc8584_csr_write(bus, phy0, 0x0fe8, 0x0091b06c); in vsc8584_config_pre_init()
944 vsc8584_csr_write(bus, phy0, 0x0fea, 0x00041600); in vsc8584_config_pre_init()
945 vsc8584_csr_write(bus, phy0, 0x0f80, 0x00fffaff); in vsc8584_config_pre_init()
946 vsc8584_csr_write(bus, phy0, 0x0fec, 0x00901809); in vsc8584_config_pre_init()
947 vsc8584_csr_write(bus, phy0, 0x0ffe, 0x00b01007); in vsc8584_config_pre_init()
948 vsc8584_csr_write(bus, phy0, 0x16b0, 0x00eeff00); in vsc8584_config_pre_init()
949 vsc8584_csr_write(bus, phy0, 0x16b2, 0x00007000); in vsc8584_config_pre_init()
950 vsc8584_csr_write(bus, phy0, 0x16b4, 0x00000814); in vsc8584_config_pre_init()
952 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8584_config_pre_init()
955 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e); in vsc8584_config_pre_init()
957 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8584_config_pre_init()
960 vsc8584_csr_write(bus, phy0, 0x0486, 0x0008a518); in vsc8584_config_pre_init()
961 vsc8584_csr_write(bus, phy0, 0x0488, 0x006dc696); in vsc8584_config_pre_init()
962 vsc8584_csr_write(bus, phy0, 0x048a, 0x00000912); in vsc8584_config_pre_init()
964 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8584_config_pre_init()
967 reg = bus->read(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_8); in vsc8584_config_pre_init()
969 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_TEST_PAGE_8, reg); in vsc8584_config_pre_init()
971 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8584_config_pre_init()
975 reg = bus->read(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_EXT_CNTL_STATUS); in vsc8584_config_pre_init()
977 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_PHY_EXT_CNTL_STATUS, reg); in vsc8584_config_pre_init()
979 ret = vsc8584_get_fw_crc(bus, phy0, in vsc8584_config_pre_init()
988 if (vsc8584_patch_fw(bus, phy0, fw_patch_vsc8584, in vsc8584_config_pre_init()
993 vsc8584_micro_deassert_reset(bus, phy0, false); in vsc8584_config_pre_init()
995 ret = vsc8584_get_fw_crc(bus, phy0, in vsc8584_config_pre_init()
1005 ret = vsc8584_micro_assert_reset(bus, phy0); in vsc8584_config_pre_init()
1009 vsc8584_micro_deassert_reset(bus, phy0, true); in vsc8584_config_pre_init()
1012 bus->write(bus, phy0, MDIO_DEVAD_NONE, MSCC_EXT_PAGE_ACCESS, in vsc8584_config_pre_init()
1454 ret = vsc8584_cmd(phydev->bus, phydev->addr, reg_val); in vsc8584_config_init()
1461 ret = vsc8584_cmd(phydev->bus, phydev->addr, PROC_CMD_FIBER_MEDIA_CONF | in vsc8584_config_init()
1469 ret = vsc8584_cmd(phydev->bus, phydev->addr, PROC_CMD_FIBER_MEDIA_CONF | in vsc8584_config_init()