Lines Matching defs:zynq_gem_regs
135 struct zynq_gem_regs { struct
136 u32 nwctrl; /* 0x0 - Network Control reg */
137 u32 nwcfg; /* 0x4 - Network Config reg */
138 u32 nwsr; /* 0x8 - Network Status reg */
139 u32 reserved1;
140 u32 dmacr; /* 0x10 - DMA Control reg */
141 u32 txsr; /* 0x14 - TX Status reg */
142 u32 rxqbase; /* 0x18 - RX Q Base address reg */
143 u32 txqbase; /* 0x1c - TX Q Base address reg */
144 u32 rxsr; /* 0x20 - RX Status reg */
145 u32 reserved2[2];
146 u32 idr; /* 0x2c - Interrupt Disable reg */
147 u32 reserved3;
148 u32 phymntnc; /* 0x34 - Phy Maintaince reg */
149 u32 reserved4[18];
150 u32 hashl; /* 0x80 - Hash Low address reg */
151 u32 hashh; /* 0x84 - Hash High address reg */
154 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
155 u32 match[4]; /* 0xa8 - Type ID1 Match reg */
156 u32 reserved6[18];
158 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
159 u32 reserved9[20];
160 u32 pcscntrl;
161 u32 rserved12[36];
162 u32 dcfg6; /* 0x294 Design config reg6 */
163 u32 reserved7[106];
164 u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
165 u32 reserved8[15];
166 u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
167 u32 reserved10[17];
168 u32 upper_txqbase; /* 0x4C8 - Upper tx_q base addr */
169 u32 reserved11[2];
170 u32 upper_rxqbase; /* 0x4D4 - Upper rx_q base addr */